From 77b806fe7e68e853676f7c4bad14349aba1affa5 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 16 Mar 2018 17:55:18 +0530 Subject: gpu: nvgpu: gv100: fix PMA list alignment in ctxsw buffer GV100 ucode is changed so that it expects LIST_nv_perf_pma_ctx_reg list in ctxsw buffer to be 256 byte aligned but same change is not applied to other chip ucodes ADD new HAL (*add_ctxsw_reg_perf_pma) to configure PMA register list and define a common HAL gr_gk20a_add_ctxsw_reg_perf_pma() for all other chips except GV100 Define a separate HAL for GV100 gr_gv100_add_ctxsw_reg_perf_pma() and fix the required alignment in this function Bug 1998067 Change-Id: Ie172fe90e2cdbac2509f2ece953cd8552e66fc56 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1676655 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 5750fd78..7156a29d 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -221,6 +221,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_max_gfxp_wfi_timeout_count = gr_gp10b_get_max_gfxp_wfi_timeout_count, .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, + .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, }, .fb = { .reset = fb_gk20a_reset, -- cgit v1.2.2