From 447a7697e6da888b1559781148fb2a8076ab4e45 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 13 Aug 2018 14:55:04 -0700 Subject: gpu: nvgpu: Scrub gp10b vgpu HALs vgpu does not have access to registers. Go through vgpu gp10b HAL and find all functions that would access a register. Replace each of them with a NULL. Change-Id: I32e91c85f128958ba03d2b8303fa9ff11615498f Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1798507 Reviewed-by: svc-misra-checker Reviewed-by: svccoveritychecker Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 350 ++++++++++++-------------- 1 file changed, 161 insertions(+), 189 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 00efe316..070339d2 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -81,15 +81,15 @@ static const struct gpu_ops vgpu_gp10b_ops = { .ltc = { .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = gm20b_ltc_init_cbc, + .set_zbc_color_entry = NULL, + .set_zbc_depth_entry = NULL, + .init_cbc = NULL, .init_fs_state = vgpu_ltc_init_fs_state, .init_comptags = vgpu_ltc_init_comptags, .cbc_ctrl = NULL, - .isr = gp10b_ltc_isr, - .cbc_fix_config = gm20b_ltc_cbc_fix_config, - .flush = gm20b_flush_ltc, + .isr = NULL, + .cbc_fix_config = NULL, + .flush = NULL, .set_enabled = NULL, .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, @@ -98,13 +98,13 @@ static const struct gpu_ops vgpu_gp10b_ops = { .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, }, .ce2 = { - .isr_stall = gp10b_ce_isr, - .isr_nonstall = gp10b_ce_nonstall_isr, + .isr_stall = NULL, + .isr_nonstall = NULL, .get_num_pce = vgpu_ce_get_num_pce, }, .gr = { .get_patch_slots = gr_gk20a_get_patch_slots, - .init_gpc_mmu = gr_gm20b_init_gpc_mmu, + .init_gpc_mmu = NULL, .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, .cb_size_default = gr_gp10b_cb_size_default, .calc_global_ctx_buffer_size = @@ -113,21 +113,20 @@ static const struct gpu_ops vgpu_gp10b_ops = { .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, .commit_global_pagepool = gr_gp10b_commit_global_pagepool, - .handle_sw_method = gr_gp10b_handle_sw_method, - .set_alpha_circular_buffer_size = - gr_gp10b_set_alpha_circular_buffer_size, - .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, - .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, + .handle_sw_method = NULL, + .set_alpha_circular_buffer_size = NULL, + .set_circular_buffer_size = NULL, + .enable_hww_exceptions = NULL, .is_valid_class = gr_gp10b_is_valid_class, .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, .is_valid_compute_class = gr_gp10b_is_valid_compute_class, .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .init_fs_state = vgpu_gr_init_fs_state, - .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, - .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, - .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, - .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, + .set_hww_esr_report_mask = NULL, + .falcon_load_ucode = NULL, + .load_ctxsw_ucode = NULL, + .set_gpc_tpc_mask = NULL, .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, @@ -135,12 +134,12 @@ static const struct gpu_ops vgpu_gp10b_ops = { .is_tpc_addr = gr_gm20b_is_tpc_addr, .get_tpc_num = gr_gm20b_get_tpc_num, .detect_sm_arch = vgpu_gr_detect_sm_arch, - .add_zbc_color = gr_gp10b_add_zbc_color, - .add_zbc_depth = gr_gp10b_add_zbc_depth, + .add_zbc_color = NULL, + .add_zbc_depth = NULL, .zbc_set_table = vgpu_gr_add_zbc, .zbc_query_table = vgpu_gr_query_zbc, - .pmu_save_zbc = gk20a_pmu_save_zbc, - .add_zbc = gr_gk20a_add_zbc, + .pmu_save_zbc = NULL, + .add_zbc = NULL, .pagepool_default_size = gr_gp10b_pagepool_default_size, .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, @@ -155,67 +154,67 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, .get_max_fbps_count = vgpu_gr_get_max_fbps_count, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, - .wait_empty = gr_gp10b_wait_empty, + .wait_empty = NULL, .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, - .bpt_reg_info = gr_gm20b_bpt_reg_info, + .bpt_reg_info = NULL, .get_access_map = gr_gp10b_get_access_map, - .handle_fecs_error = gr_gp10b_handle_fecs_error, - .handle_sm_exception = gr_gp10b_handle_sm_exception, - .handle_tex_exception = gr_gp10b_handle_tex_exception, - .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, - .enable_exceptions = gk20a_gr_enable_exceptions, - .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .handle_fecs_error = NULL, + .handle_sm_exception = NULL, + .handle_tex_exception = NULL, + .enable_gpc_exceptions = NULL, + .enable_exceptions = NULL, + .get_lrf_tex_ltc_dram_override = NULL, .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, .record_sm_error_state = gm20b_gr_record_sm_error_state, - .update_sm_error_state = gm20b_gr_update_sm_error_state, + .update_sm_error_state = NULL, .clear_sm_error_state = vgpu_gr_clear_sm_error_state, .suspend_contexts = vgpu_gr_suspend_contexts, .resume_contexts = vgpu_gr_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .init_sm_id_table = vgpu_gr_init_sm_id_table, - .load_smid_config = gr_gp10b_load_smid_config, - .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, - .setup_rop_mapping = gr_gk20a_setup_rop_mapping, - .program_zcull_mapping = gr_gk20a_program_zcull_mapping, - .commit_global_timeslice = gr_gk20a_commit_global_timeslice, + .load_smid_config = NULL, + .program_sm_id_numbering = NULL, + .setup_rop_mapping = NULL, + .program_zcull_mapping = NULL, + .commit_global_timeslice = NULL, .commit_inst = vgpu_gr_commit_inst, .write_zcull_ptr = gr_gk20a_write_zcull_ptr, .write_pm_ptr = gr_gk20a_write_pm_ptr, - .load_tpc_mask = gr_gm20b_load_tpc_mask, - .trigger_suspend = gr_gk20a_trigger_suspend, + .load_tpc_mask = NULL, + .trigger_suspend = NULL, .wait_for_pause = gr_gk20a_wait_for_pause, - .resume_from_pause = gr_gk20a_resume_from_pause, + .resume_from_pause = NULL, .clear_sm_errors = gr_gk20a_clear_sm_errors, - .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .tpc_enabled_exceptions = NULL, .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, - .sm_debugger_attached = gk20a_gr_sm_debugger_attached, - .suspend_single_sm = gk20a_gr_suspend_single_sm, - .suspend_all_sms = gk20a_gr_suspend_all_sms, - .resume_single_sm = gk20a_gr_resume_single_sm, - .resume_all_sms = gk20a_gr_resume_all_sms, - .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, - .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, + .sm_debugger_attached = NULL, + .suspend_single_sm = NULL, + .suspend_all_sms = NULL, + .resume_single_sm = NULL, + .resume_all_sms = NULL, + .get_sm_hww_warp_esr = NULL, + .get_sm_hww_global_esr = NULL, .get_sm_no_lock_down_hww_global_esr_mask = gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, - .lock_down_sm = gk20a_gr_lock_down_sm, - .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, - .clear_sm_hww = gm20b_gr_clear_sm_hww, + .lock_down_sm = NULL, + .wait_for_sm_lock_down = NULL, + .clear_sm_hww = NULL, .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, - .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .disable_rd_coalesce = NULL, .set_boosted_ctx = NULL, .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, - .set_czf_bypass = gr_gp10b_set_czf_bypass, + .set_czf_bypass = NULL, .init_czf_bypass = gr_gp10b_init_czf_bypass, - .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, + .pre_process_sm_exception = NULL, .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, - .init_preemption_state = gr_gp10b_init_preemption_state, + .init_preemption_state = NULL, .update_boosted_ctx = NULL, - .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, - .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, + .set_bes_crop_debug3 = NULL, + .set_bes_crop_debug4 = NULL, .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, @@ -237,71 +236,46 @@ static const struct gpu_ops vgpu_gp10b_ops = { gr_gk20a_get_offset_in_gpccs_segment, }, .fb = { - .reset = fb_gk20a_reset, - .init_hw = gk20a_fb_init_hw, - .init_fs_state = fb_gm20b_init_fs_state, - .set_mmu_page_size = gm20b_fb_set_mmu_page_size, - .set_use_full_comp_tag_line = - gm20b_fb_set_use_full_comp_tag_line, + .reset = NULL, + .init_hw = NULL, + .init_fs_state = NULL, + .set_mmu_page_size = NULL, + .set_use_full_comp_tag_line = NULL, .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, - .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, - .read_wpr_info = gm20b_fb_read_wpr_info, + .vpr_info_fetch = NULL, + .dump_vpr_wpr_info = NULL, + .read_wpr_info = NULL, .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, .tlb_invalidate = vgpu_mm_tlb_invalidate, }, .clock_gating = { - .slcg_bus_load_gating_prod = - gp10b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gp10b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gp10b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gp10b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gp10b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gp10b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gp10b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gp10b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gp10b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gp10b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gp10b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gp10b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gp10b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gp10b_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gp10b_blcg_ce_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gp10b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gp10b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gp10b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gp10b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gp10b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gp10b_blcg_pwr_csb_load_gating_prod, - .blcg_pmu_load_gating_prod = - gp10b_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gp10b_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gp10b_pg_gr_load_gating_prod, + .slcg_bus_load_gating_prod = NULL, + .slcg_ce2_load_gating_prod = NULL, + .slcg_chiplet_load_gating_prod = NULL, + .slcg_ctxsw_firmware_load_gating_prod = NULL, + .slcg_fb_load_gating_prod = NULL, + .slcg_fifo_load_gating_prod = NULL, + .slcg_gr_load_gating_prod = NULL, + .slcg_ltc_load_gating_prod = NULL, + .slcg_perf_load_gating_prod = NULL, + .slcg_priring_load_gating_prod = NULL, + .slcg_pmu_load_gating_prod = NULL, + .slcg_therm_load_gating_prod = NULL, + .slcg_xbar_load_gating_prod = NULL, + .blcg_bus_load_gating_prod = NULL, + .blcg_ce_load_gating_prod = NULL, + .blcg_ctxsw_firmware_load_gating_prod = NULL, + .blcg_fb_load_gating_prod = NULL, + .blcg_fifo_load_gating_prod = NULL, + .blcg_gr_load_gating_prod = NULL, + .blcg_ltc_load_gating_prod = NULL, + .blcg_pwr_csb_load_gating_prod = NULL, + .blcg_pmu_load_gating_prod = NULL, + .blcg_xbar_load_gating_prod = NULL, + .pg_gr_load_gating_prod = NULL, }, .fifo = { .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, @@ -326,8 +300,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { .tsg_verify_status_ctx_reload = NULL, .reschedule_runlist = NULL, .update_runlist = vgpu_fifo_update_runlist, - .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, - .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, .get_mmu_fault_client_desc = gp10b_fifo_get_mmu_fault_client_desc, .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, @@ -346,16 +320,16 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, - .dump_pbdma_status = gk20a_dump_pbdma_status, - .dump_eng_status = gk20a_dump_eng_status, - .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, + .dump_pbdma_status = NULL, + .dump_eng_status = NULL, + .dump_channel_status_ramfc = NULL, .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, - .is_preempt_pending = gk20a_fifo_is_preempt_pending, + .is_preempt_pending = NULL, .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, - .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, - .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, - .handle_sched_error = gk20a_fifo_handle_sched_error, - .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, + .reset_enable_hw = NULL, + .teardown_ch_tsg = NULL, + .handle_sched_error = NULL, + .handle_pbdma_intr_0 = NULL, .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, .tsg_bind_channel = vgpu_tsg_bind_channel, .tsg_unbind_channel = vgpu_tsg_unbind_channel, @@ -380,8 +354,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { #endif .resetup_ramfc = NULL, .device_info_fault_id = top_device_info_data_fault_id_enum_v, - .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, - .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, + .runlist_hw_submit = NULL, + .runlist_wait_pending = NULL, .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, @@ -418,7 +392,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .fb_flush = vgpu_mm_fb_flush, .l2_invalidate = vgpu_mm_l2_invalidate, .l2_flush = vgpu_mm_l2_flush, - .cbc_clean = gk20a_mm_cbc_clean, + .cbc_clean = NULL, .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, @@ -429,44 +403,44 @@ static const struct gpu_ops vgpu_gp10b_ops = { .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, .is_bar1_supported = gm20b_mm_is_bar1_supported, .init_inst_block = gk20a_init_inst_block, - .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + .mmu_fault_pending = NULL, .init_bar2_vm = gp10b_init_bar2_vm, .remove_bar2_vm = gp10b_remove_bar2_vm, .get_kind_invalid = gm20b_get_kind_invalid, .get_kind_pitch = gm20b_get_kind_pitch, }, .pramin = { - .data032_r = pram_data032_r, + .data032_r = NULL, }, .therm = { - .init_therm_setup_hw = gp10b_init_therm_setup_hw, - .init_elcg_mode = gm20b_therm_init_elcg_mode, - .init_blcg_mode = gm20b_therm_init_blcg_mode, - .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, + .init_therm_setup_hw = NULL, + .init_elcg_mode = NULL, + .init_blcg_mode = NULL, + .elcg_init_idle_filters = NULL, }, .pmu = { - .pmu_setup_elpg = gp10b_pmu_setup_elpg, - .pmu_get_queue_head = pwr_pmu_queue_head_r, - .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, - .pmu_get_queue_tail = pwr_pmu_queue_tail_r, - .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, - .pmu_queue_head = gk20a_pmu_queue_head, - .pmu_queue_tail = gk20a_pmu_queue_tail, - .pmu_msgq_tail = gk20a_pmu_msgq_tail, - .pmu_mutex_size = pwr_pmu_mutex__size_1_v, - .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, - .pmu_mutex_release = gk20a_pmu_mutex_release, - .write_dmatrfbase = gp10b_write_dmatrfbase, - .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, - .pmu_init_perfmon = nvgpu_pmu_init_perfmon, - .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, - .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, - .pmu_pg_init_param = gp10b_pg_gr_init, - .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, - .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, - .dump_secure_fuses = pmu_dump_security_fuses_gm20b, - .reset_engine = gk20a_pmu_engine_reset, - .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, + .pmu_setup_elpg = NULL, + .pmu_get_queue_head = NULL, + .pmu_get_queue_head_size = NULL, + .pmu_get_queue_tail = NULL, + .pmu_get_queue_tail_size = NULL, + .pmu_queue_head = NULL, + .pmu_queue_tail = NULL, + .pmu_msgq_tail = NULL, + .pmu_mutex_size = NULL, + .pmu_mutex_acquire = NULL, + .pmu_mutex_release = NULL, + .write_dmatrfbase = NULL, + .pmu_elpg_statistics = NULL, + .pmu_init_perfmon = NULL, + .pmu_perfmon_start_sampling = NULL, + .pmu_perfmon_stop_sampling = NULL, + .pmu_pg_init_param = NULL, + .pmu_pg_supported_engines_list = NULL, + .pmu_pg_engines_feature_list = NULL, + .dump_secure_fuses = NULL, + .reset_engine = NULL, + .is_engine_in_reset = NULL, }, .regops = { .exec_regops = vgpu_exec_regops, @@ -493,23 +467,23 @@ static const struct gpu_ops vgpu_gp10b_ops = { .apply_smpc_war = gp10b_apply_smpc_war, }, .mc = { - .intr_mask = mc_gp10b_intr_mask, - .intr_enable = mc_gp10b_intr_enable, - .intr_unit_config = mc_gp10b_intr_unit_config, - .isr_stall = mc_gp10b_isr_stall, - .intr_stall = mc_gp10b_intr_stall, - .intr_stall_pause = mc_gp10b_intr_stall_pause, - .intr_stall_resume = mc_gp10b_intr_stall_resume, - .intr_nonstall = mc_gp10b_intr_nonstall, - .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, - .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, - .isr_nonstall = mc_gk20a_isr_nonstall, - .enable = gk20a_mc_enable, - .disable = gk20a_mc_disable, - .reset = gk20a_mc_reset, - .boot_0 = gk20a_mc_boot_0, - .is_intr1_pending = mc_gp10b_is_intr1_pending, - .log_pending_intrs = mc_gp10b_log_pending_intrs, + .intr_mask = NULL, + .intr_enable = NULL, + .intr_unit_config = NULL, + .isr_stall = NULL, + .intr_stall = NULL, + .intr_stall_pause = NULL, + .intr_stall_resume = NULL, + .intr_nonstall = NULL, + .intr_nonstall_pause = NULL, + .intr_nonstall_resume = NULL, + .isr_nonstall = NULL, + .enable = NULL, + .disable = NULL, + .reset = NULL, + .boot_0 = NULL, + .is_intr1_pending = NULL, + .log_pending_intrs = NULL, }, .debug = { .show_dump = NULL, @@ -529,11 +503,11 @@ static const struct gpu_ops vgpu_gp10b_ops = { .perfbuffer_disable = vgpu_perfbuffer_disable, }, .bus = { - .init_hw = gk20a_bus_init_hw, - .isr = gk20a_bus_isr, + .init_hw = NULL, + .isr = NULL, .bar1_bind = NULL, .bar2_bind = NULL, - .set_bar0_window = gk20a_bus_set_bar0_window, + .set_bar0_window = NULL, }, .ptimer = { .isr = NULL, @@ -555,24 +529,22 @@ static const struct gpu_ops vgpu_gp10b_ops = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .priv_ring = { - .enable_priv_ring = gm20b_priv_ring_enable, - .isr = gp10b_priv_ring_isr, - .set_ppriv_timeout_settings = - gm20b_priv_set_timeout_settings, - .enum_ltc = gm20b_priv_ring_enum_ltc, + .enable_priv_ring = NULL, + .isr = NULL, + .set_ppriv_timeout_settings = NULL, + .enum_ltc = NULL, }, .fuse = { .check_priv_security = vgpu_gp10b_fuse_check_priv_security, - .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, - .is_opt_feature_override_disable = - gp10b_fuse_is_opt_feature_override_disable, - .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, - .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, - .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, - .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, - .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, - .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, - .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, + .is_opt_ecc_enable = NULL, + .is_opt_feature_override_disable = NULL, + .fuse_status_opt_fbio = NULL, + .fuse_status_opt_fbp = NULL, + .fuse_status_opt_rop_l2_fbp = NULL, + .fuse_status_opt_tpc_gpc = NULL, + .fuse_ctrl_opt_tpc_gpc = NULL, + .fuse_opt_sec_debug_en = NULL, + .fuse_opt_priv_sec_en = NULL, .read_vin_cal_fuse_rev = NULL, .read_vin_cal_slope_intercept_fuse = NULL, .read_vin_cal_gain_offset_fuse = NULL, -- cgit v1.2.2