From c5810a670d367ae1dc405fcc3108e11265df34bb Mon Sep 17 00:00:00 2001 From: aalex Date: Fri, 7 Sep 2018 22:08:05 +0530 Subject: gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl added hal layer for SM exception mask handling for taking care of vitualization case. Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544 Signed-off-by: aalex Reviewed-on: https://git-master.nvidia.com/r/1816284 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.h') diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index 20205d3c..ecaaaf23 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h @@ -61,5 +61,5 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); int vgpu_enable_tsg(struct tsg_gk20a *tsg); - +int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask); #endif -- cgit v1.2.2