From 47e3d2e90511b1cba68e46233896a918b32b5d33 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Thu, 21 Apr 2016 16:35:44 -0700 Subject: gpu: nvgpu: fix engine reset in FECS trace In virtualization case, VM server is the only one allowed to write to ctxsw ring buffer. It will also generate an event in case of engine reset. Only generate a tracepoint on Guest OS side. EVLR-314 Change-Id: I2cb09780a9b41237fe196ef1f3515923f36a24a4 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1130743 (cherry picked from commit 4bbf9538e2a3375eb86b2feea6c605c3eec2ca40) Reviewed-on: http://git-master/r/1133614 (cherry picked from commit 2076d944db41b37143c27795b3cffd88e99e0b00) Reviewed-on: http://git-master/r/1150046 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c') diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 83fd65ff..8fcc7cc1 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -630,7 +630,7 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u", info->type, info->chid); - gk20a_ctxsw_trace_channel_reset(g, ch); + trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); switch (info->type) { case TEGRA_VGPU_FIFO_INTR_PBDMA: -- cgit v1.2.2