From b3a7c2b305ec6f895dc236f0c5f163bd4cbeb248 Mon Sep 17 00:00:00 2001 From: Sachit Kadle Date: Tue, 24 Jan 2017 10:22:13 -0800 Subject: gpu: nvgpu: vgpu: add devfreq support Add devfreq governor support in order to allow frequency scaling in virtualization config. GPU clock frequency operations are re-directed to the server over RPC. Bug 200237433 Change-Id: I1c8e565a4fff36d3456dc72ebb20795b7822650e Signed-off-by: Sachit Kadle Reviewed-on: http://git-master/r/1295542 (cherry picked from commit d5c956fc06697eda3829c67cb22987e538213b29) Reviewed-on: http://git-master/r/1280968 (cherry picked from commit 25e2b3cf7cb5559a6849c0024d42c157564a9be2) Reviewed-on: http://git-master/r/1321835 (cherry picked from commit f871b52fd3f553d6b6375a3c848fbca272ed8e29) Reviewed-on: http://git-master/r/1313468 Tested-by: Aparna Das Reviewed-by: Terje Bergstrom Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/vgpu/clk_vgpu.c | 130 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 drivers/gpu/nvgpu/vgpu/clk_vgpu.c (limited to 'drivers/gpu/nvgpu/vgpu/clk_vgpu.c') diff --git a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c new file mode 100644 index 00000000..fe5533b6 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c @@ -0,0 +1,130 @@ +/* + * Virtualized GPU Clock Interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu/vgpu.h" +#include "vgpu/clk_vgpu.h" + +static unsigned long +vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; + +static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain) +{ + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; + int err; + unsigned long ret = 0; + + gk20a_dbg_fn(""); + + switch (api_domain) { + case CTRL_CLK_DOMAIN_GPCCLK: + msg.cmd = TEGRA_VGPU_CMD_GET_GPU_CLK_RATE; + msg.handle = vgpu_get_handle(g); + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) + nvgpu_err(g, "%s failed - %d", __func__, err); + else + /* return frequency in Hz */ + ret = p->rate * 1000; + break; + case CTRL_CLK_DOMAIN_PWRCLK: + nvgpu_err(g, "unsupported clock: %u", api_domain); + break; + default: + nvgpu_err(g, "unknown clock: %u", api_domain); + break; + } + + return ret; +} + +static int vgpu_clk_set_rate(struct gk20a *g, + u32 api_domain, unsigned long rate) +{ + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; + int err = -EINVAL; + + gk20a_dbg_fn(""); + + switch (api_domain) { + case CTRL_CLK_DOMAIN_GPCCLK: + msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE; + msg.handle = vgpu_get_handle(g); + + /* server dvfs framework requires frequency in kHz */ + p->rate = (u32)(rate / 1000); + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) + nvgpu_err(g, "%s failed - %d", __func__, err); + break; + case CTRL_CLK_DOMAIN_PWRCLK: + nvgpu_err(g, "unsupported clock: %u", api_domain); + break; + default: + nvgpu_err(g, "unknown clock: %u", api_domain); + break; + } + + return err; +} + +void vgpu_init_clk_support(struct gk20a *g) +{ + g->ops.clk.get_rate = vgpu_clk_get_rate; + g->ops.clk.set_rate = vgpu_clk_set_rate; +} + +long vgpu_clk_round_rate(struct device *dev, unsigned long rate) +{ + /* server will handle frequency rounding */ + return rate; +} + +int vgpu_clk_get_freqs(struct device *dev, + unsigned long **freqs, int *num_freqs) +{ + struct gk20a_platform *platform = gk20a_get_platform(dev); + struct gk20a *g = platform->g; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_get_gpu_freq_table_params *p = + &msg.params.get_gpu_freq_table; + unsigned int i; + int err; + + gk20a_dbg_fn(""); + + msg.cmd = TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE; + msg.handle = vgpu_get_handle(g); + + p->num_freqs = TEGRA_VGPU_GPU_FREQ_TABLE_SIZE; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(g, "%s failed - %d", __func__, err); + return err; + } + + /* return frequency in Hz */ + for (i = 0; i < p->num_freqs; i++) + vgpu_freq_table[i] = p->freqs[i] * 1000; + + *freqs = vgpu_freq_table; + *num_freqs = p->num_freqs; + + return 0; +} -- cgit v1.2.2