From 3d9c33c5953e383527c7e4af594adfe0c82b5788 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 13 Sep 2016 14:23:45 -0700 Subject: gpu: nvgpu: clk arbiter skeleton Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/pstate/pstate.c | 40 ++++++++++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/pstate/pstate.h | 9 ++++++++- 2 files changed, 47 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/pstate') diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index e9b9775e..0dc15201 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c @@ -234,7 +234,7 @@ static int parse_pstate_entry_5x(struct gk20a *g, memset(pstate, 0, sizeof(struct pstate)); pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X; pstate->num = 0x0F - entry->pstate_level; - pstate->clklist.clksetinfolistsize = hdr->clock_entry_count; + pstate->clklist.num_info = hdr->clock_entry_count; gk20a_dbg_info("pstate P%u", pstate->num); @@ -357,3 +357,41 @@ static int pstate_sw_setup(struct gk20a *g) done: return err; } + +static struct pstate *pstate_find(struct gk20a *g, u32 num) +{ + struct pstates *pstates = &(g->perf_pmu.pstatesobjs); + struct pstate *pstate; + u8 i; + + gk20a_dbg_info("pstates = %p", pstates); + + BOARDOBJGRP_FOR_EACH(&pstates->super.super, + struct pstate *, pstate, i) { + gk20a_dbg_info("pstate=%p num=%u (looking for num=%u)", + pstate, pstate->num, num); + if (pstate->num == num) + return pstate; + } + return NULL; +} + +struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, + u32 pstate_num, enum nv_pmu_clk_clkwhich clkwhich) +{ + struct pstate *pstate = pstate_find(g, pstate_num); + struct clk_set_info *info; + u32 clkidx; + + gk20a_dbg_info("pstate = %p", pstate); + + if (!pstate) + return NULL; + + for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) { + info = &pstate->clklist.clksetinfo[clkidx]; + if (info->clkwhich == clkwhich) + return info; + } + return NULL; +} diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h index 11fa4c77..4ae72aa9 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.h +++ b/drivers/gpu/nvgpu/pstate/pstate.h @@ -20,6 +20,10 @@ #define CTRL_PERF_PSTATE_TYPE_3X 0x3 +#define CTRL_PERF_PSTATE_P0 0 +#define CTRL_PERF_PSTATE_P5 5 +#define CTRL_PERF_PSTATE_P8 8 + #define CLK_SET_INFO_MAX_SIZE (32) struct clk_set_info { @@ -30,7 +34,7 @@ struct clk_set_info { }; struct clk_set_info_list { - u32 clksetinfolistsize; + u32 num_info; struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE]; }; @@ -48,4 +52,7 @@ struct pstates { int gk20a_init_pstate_support(struct gk20a *g); int gk20a_init_pstate_pmu_support(struct gk20a *g); +struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num, + enum nv_pmu_clk_clkwhich clkwhich); + #endif /* __PSTATE_H__ */ -- cgit v1.2.2