From db529935a5f50e9e683d44d2eb01d0d76a915792 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Thu, 8 Sep 2016 17:35:13 -0700 Subject: gpu: nvgpu: parse performance table Parse VBIOS performance table to retrieve clock ranges. Jira DNVGPU-125 Change-Id: Ia8e4ede158de5c5374205a510099d00b497fe1a6 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1218935 (cherry picked from commit b5b7c789e98a20eb4cc5c30f0e2eb45d4a882cc4) Reviewed-on: http://git-master/r/1232593 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/pstate/pstate.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/nvgpu/pstate/pstate.h') diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h index fb49adf3..11fa4c77 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.h +++ b/drivers/gpu/nvgpu/pstate/pstate.h @@ -12,8 +12,40 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ +#ifndef __PSTATE_H__ +#define __PSTATE_H__ #include "gk20a/gk20a.h" +#include "clk/clk.h" + +#define CTRL_PERF_PSTATE_TYPE_3X 0x3 + +#define CLK_SET_INFO_MAX_SIZE (32) + +struct clk_set_info { + enum nv_pmu_clk_clkwhich clkwhich; + u32 nominal_mhz; + u32 min_mhz; + u32 max_mhz; +}; + +struct clk_set_info_list { + u32 clksetinfolistsize; + struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE]; +}; + +struct pstate { + struct boardobj super; + u32 num; + struct clk_set_info_list clklist; +}; + +struct pstates { + struct boardobjgrp_e32 super; + u32 num_levels; +}; int gk20a_init_pstate_support(struct gk20a *g); int gk20a_init_pstate_pmu_support(struct gk20a *g); + +#endif /* __PSTATE_H__ */ -- cgit v1.2.2