From b17d9708c9e9930778de43de1edf1385acb13ebd Mon Sep 17 00:00:00 2001 From: Vijayakumar Subbu Date: Wed, 27 Jul 2016 22:29:15 -0700 Subject: gpu: nvgpu: Add dGPU clocks support JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar Signed-off-by: Vijayakumar Subbu Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/pmuif/gpmuifbios.h | 41 +++ drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h | 196 +++++++++++++++ drivers/gpu/nvgpu/pmuif/gpmuifclk.h | 414 +++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/pmuif/gpmuifperf.h | 116 +++++++++ drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h | 220 ++++++++++++++++ drivers/gpu/nvgpu/pmuif/gpmuifvolt.h | 33 +++ 6 files changed, 1020 insertions(+) create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifbios.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifclk.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifperf.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifvolt.h (limited to 'drivers/gpu/nvgpu/pmuif') diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifbios.h b/drivers/gpu/nvgpu/pmuif/gpmuifbios.h new file mode 100644 index 00000000..2581d3fa --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifbios.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFBIOS_H_ +#define _GPMUIFBIOS_H_ + +struct nv_pmu_bios_vfield_register_segment_super { + u8 type; + u8 low_bit; + u8 high_bit; +}; + +struct nv_pmu_bios_vfield_register_segment_reg { + struct nv_pmu_bios_vfield_register_segment_super super; + u32 addr; +}; + +struct nv_pmu_bios_vfield_register_segment_index_reg { + struct nv_pmu_bios_vfield_register_segment_super super; + u32 addr; + u32 reg_index; + u32 index; +}; + +union nv_pmu_bios_vfield_register_segment { + struct nv_pmu_bios_vfield_register_segment_super super; + struct nv_pmu_bios_vfield_register_segment_reg reg; + struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; +}; + + +#endif /* _GPMUIFBIOS_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h new file mode 100644 index 00000000..7a061472 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h @@ -0,0 +1,196 @@ +/* +* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ +#ifndef _GPMUIFBOARDOBJ_H_ +#define _GPMUIFBOARDOBJ_H_ + +#include "gk20a/gk20a.h" +#include "gk20a/pmu_gk20a.h" +#include "ctrl/ctrlboardobj.h" + +/* + * Base structure describing a BOARDOBJ for communication between Kernel and + * PMU. + */ +struct nv_pmu_boardobj { + u8 type; +}; + +/* + * Base structure describing a BOARDOBJ for Query interface between Kernel and + * PMU. + */ +struct nv_pmu_boardobj_query { + u8 type; +}; + +/* + * Virtual base structure describing a BOARDOBJGRP interface between Kernel and + * PMU. + */ +struct nv_pmu_boardobjgrp_super { + u8 type; + u8 class_id; + u8 obj_slots; + u8 rsvd; +}; + +struct nv_pmu_boardobjgrp { + struct nv_pmu_boardobjgrp_super super; + u32 obj_mask; +}; + +struct nv_pmu_boardobjgrp_e32 { + struct nv_pmu_boardobjgrp_super super; + struct ctrl_boardobjgrp_mask_e32 obj_mask; +}; + +struct nv_pmu_boardobjgrp_e255 { + struct nv_pmu_boardobjgrp_super super; + struct ctrl_boardobjgrp_mask_e255 obj_mask; +}; + +struct nv_pmu_boardobj_cmd_grp_payload { + struct pmu_allocation_v3 dmem_buf; + struct flcn_mem_desc_v0 fb; + u8 hdr_size; + u8 entry_size; +}; + +struct nv_pmu_boardobj_cmd_grp { + u8 cmd_type; + u8 pad[2]; + u8 class_id; + struct nv_pmu_boardobj_cmd_grp_payload grp; +}; + +#define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \ + (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp)) + +struct nv_pmu_boardobj_cmd { + union { + u8 cmd_type; + struct nv_pmu_boardobj_cmd_grp grp; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +struct nv_pmu_boardobj_msg_grp { + u8 msg_type; + bool b_success; + flcn_status flcn_status; + u8 class_id; +}; + +struct nv_pmu_boardobj_msg { + union { + u8 msg_type; + struct nv_pmu_boardobj_msg_grp grp; + struct nv_pmu_boardobj_msg_grp grp_set; + struct nv_pmu_boardobj_msg_grp grp_get_status; + }; +}; + +/* +* Macro generating structures describing classes which implement +* NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +* @param _slots Max number of elements this group can contain. +*/ +#define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \ + NV_PMU_MAKE_ALIGNED_STRUCT( \ + nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \ + NV_PMU_MAKE_ALIGNED_UNION( \ + nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \ + struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \ + union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \ + union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\ + } + +/* +* Macro generating structures describing classes which implement +* NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) + +/* +* Macro generating structures describing classes which implement +* NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) + +/* +* Macro generating structures for querying dynamic state for classes which +* implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS +* interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +* @param _slots Max number of elements this group can contain. +*/ +#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \ + NV_PMU_MAKE_ALIGNED_STRUCT( \ + nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \ + NV_PMU_MAKE_ALIGNED_UNION( \ + nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \ + struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \ + union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \ + hdr; \ + union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \ + objects[(_slots)]; \ + } + +/* +* Macro generating structures for querying dynamic state for classes which +* implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS +* interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) + +/* +* Macro generating structures for querying dynamic state for classes which +* implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS +* interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) + + +#endif /* _GPMUIFBOARDOBJ_H_ */ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h new file mode 100644 index 00000000..36b9aace --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h @@ -0,0 +1,414 @@ +/* +* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _GPMUIFCLK_H_ +#define _GPMUIFCLK_H_ + +#include "gk20a/gk20a.h" +#include "gk20a/pmu_gk20a.h" +#include "ctrl/ctrlboardobj.h" +#include "ctrl/ctrlvolt.h" +#include "ctrl/ctrlperf.h" +#include "ctrl/ctrlclk.h" +#include "pmuif/gpmuifboardobj.h" +#include "pmuif/gpmuifvolt.h" +#include "gk20a/pmu_common.h" + +enum nv_pmu_clk_clkwhich { + clkwhich_mclk = 5, + clkwhich_dispclk = 7, + clkwhich_gpc2clk = 17, + clkwhich_xbar2clk = 19, + clkwhich_sys2clk = 20, + clkwhich_hub2clk = 21, + clkwhich_pwrclk = 24, + clkwhich_nvdclk = 25, + clkwhich_pciegenclk = 31, +}; + +/* + * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" + * argument for communications between Kernel and PMU via the various generic + * BOARDOBJGRP interfaces. + */ +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 + +/*! +* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the +* CLK_DOMAIN feature. +*/ +struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + u32 vbios_domains; + struct ctrl_boardobjgrp_mask_e32 master_domains_mask; + u16 cntr_sampling_periodms; + bool b_override_o_v_o_c; + bool b_debug_mode; + bool b_enforce_vf_monotonicity; + u8 volt_rails_max; + struct ctrl_clk_clk_delta deltas; +}; + +struct nv_pmu_clk_clk_domain_boardobj_set { + struct nv_pmu_boardobj super; + enum nv_pmu_clk_clkwhich domain; + u32 api_domain; + u8 perf_domain_grp_idx; +}; + +struct nv_pmu_clk_clk_domain_3x_boardobj_set { + struct nv_pmu_clk_clk_domain_boardobj_set super; + bool b_noise_aware_capable; +}; + +struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_boardobj_set super; + u16 freq_mhz; +}; + +struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_boardobj_set super; + u8 clk_prog_idx_first; + u8 clk_prog_idx_last; + u8 noise_unaware_ordering_index; + u8 noise_aware_ordering_index; + bool b_force_noise_unaware_ordering; + int factory_offset_khz; + short freq_delta_min_mhz; + short freq_delta_max_mhz; + struct ctrl_clk_clk_delta deltas; +}; + +struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; + u32 slave_idxs_mask; +}; + +struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; + u8 master_idx; +}; + +union nv_pmu_clk_clk_domain_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_domain_boardobj_set super; + struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; + struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; + struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; + struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; + struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); + +struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e255 super; + u8 slave_entry_count; + u8 vf_entry_count; +}; + +struct nv_pmu_clk_clk_prog_boardobj_set { + struct nv_pmu_boardobj super; +}; + +struct nv_pmu_clk_clk_prog_1x_boardobj_set { + struct nv_pmu_clk_clk_prog_boardobj_set super; + u8 source; + u16 freq_max_mhz; + union ctrl_clk_clk_prog_1x_source_data source_data; +}; + +struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { + struct nv_pmu_clk_clk_prog_1x_boardobj_set super; + bool b_o_c_o_v_enabled; + struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ + CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; + struct ctrl_clk_clk_delta deltas; +}; + +struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { + struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; + struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ + CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; +}; + +struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { + struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; + struct ctrl_clk_clk_prog_1x_master_table_slave_entry + slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; +}; + +union nv_pmu_clk_clk_prog_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_prog_boardobj_set super; + struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; + struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; + struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; + struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); + +struct nv_pmu_clk_lut_device_desc { + u8 vselect_mode; + u16 hysteresis_threshold; +}; + +struct nv_pmu_clk_regime_desc { + u8 regime_id; + u16 fixed_freq_regime_limit_mhz; +}; + +struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; + u32 lut_step_size_uv; + u32 lut_min_voltage_uv; + u8 lut_num_entries; + u16 max_min_freq_mhz; +}; + +struct nv_pmu_clk_clk_fll_device_boardobj_set { + struct nv_pmu_boardobj super; + u8 id; + u8 mdiv; + u8 vin_idx_logic; + u8 vin_idx_sram; + u8 rail_idx_for_lut; + u16 input_freq_mhz; + u32 clk_domain; + struct nv_pmu_clk_lut_device_desc lut_device; + struct nv_pmu_clk_regime_desc regime_desc; + u8 min_freq_vfe_idx; + u8 freq_ctrl_idx; + struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; +}; + +union nv_pmu_clk_clk_fll_device_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_fll_device_boardobj_set super; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); + +struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + bool b_vin_is_disable_allowed; +}; + +struct nv_pmu_clk_clk_vin_device_boardobj_set { + struct nv_pmu_boardobj super; + u8 id; + u8 volt_domain; + u32 slope; + u32 intercept; + u32 flls_shared_mask; +}; + +union nv_pmu_clk_clk_vin_device_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_vin_device_boardobj_set super; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); + +struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e255 super; +}; + +struct nv_pmu_clk_clk_vf_point_boardobj_set { + struct nv_pmu_boardobj super; + u8 vfe_equ_idx; + u8 volt_rail_idx; +}; + +struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { + struct nv_pmu_clk_clk_vf_point_boardobj_set super; + u16 freq_mhz; + int volt_delta_uv; +}; + +struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { + struct nv_pmu_clk_clk_vf_point_boardobj_set super; + u32 source_voltage_uv; + u8 vf_gain_vfe_equ_idx; + u8 clk_domain_idx; + int freq_delta_khz; +}; + +union nv_pmu_clk_clk_vf_point_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_vf_point_boardobj_set super; + struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; + struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); + +struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e255 super; +}; + +struct nv_pmu_clk_clk_vf_point_boardobj_get_status { + struct nv_pmu_boardobj super; + struct ctrl_clk_vf_pair pair; +}; + +struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { + struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; + u16 vf_gain_value; +}; + +union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; + struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); + +#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) + +struct nv_pmu_clk_clk_domain_list { + u8 num_domains; + struct ctrl_clk_clk_domain_list_item clk_domains[ + NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; +}; + +struct nv_pmu_clk_vf_change_inject { + u8 flags; + struct nv_pmu_clk_clk_domain_list clk_list; + struct nv_pmu_volt_volt_rail_list volt_list; +}; + +#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) +#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) + +struct nv_pmu_clk_load_payload_freq_controllers { + struct ctrl_boardobjgrp_mask_e32 load_mask; +}; + +struct nv_pmu_clk_load { + u8 feature; + u32 action_mask; + union { + struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; + } payload; +}; + +/* CLK CMD ID definitions. */ +#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) +#define NV_PMU_CLK_CMD_ID_RPC (0x00000001) +#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) + +#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) +#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) + +struct nv_pmu_clk_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ + (offsetof(struct nv_pmu_clk_cmd_rpc, request)) + +struct nv_pmu_clk_cmd { + union { + u8 cmd_type; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_clk_cmd_rpc rpc; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +struct nv_pmu_clk_rpc { + u8 function; + bool b_supported; + bool b_success; + flcn_status flcn_status; + union { + struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; + struct nv_pmu_clk_load clk_load; + } params; +}; + +/* CLK MSG ID definitions */ +#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) +#define NV_PMU_CLK_MSG_ID_RPC (0x00000001) +#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) + +struct nv_pmu_clk_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_clk_msg_rpc, response) + +struct nv_pmu_clk_msg { + union { + u8 msg_type; + struct nv_pmu_boardobj_msg_grp grp_set; + struct nv_pmu_clk_msg_rpc rpc; + struct nv_pmu_boardobj_msg_grp grp_get_status; + }; +}; + +struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_clk_clk_vin_device_boardobj_get_status { + struct nv_pmu_boardobj_query super; + u32 actual_voltage_uv; + u32 corrected_voltage_uv; + u8 sampled_code; + u8 override_code; +}; + +union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); + +struct nv_pmu_clk_lut_vf_entry { + u32 entry; +}; + +struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_clk_clk_fll_device_boardobj_get_status { + struct nv_pmu_boardobj_query super; + u8 current_regime_id; + u16 min_freq_mhz; + struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; +}; + +union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); + +#endif /*_GPMUIFCLK_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h new file mode 100644 index 00000000..b1d2f3fd --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPERF_H_ +#define _GPMUIFPERF_H_ + +#include "gpmuifvolt.h" +#include "gpmuifperfvfe.h" + +/* +* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId" +* argument for communications between Kernel and PMU via the various generic +* BOARDOBJGRP interfaces. +*/ +#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 +#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 + +#define NV_PMU_PERF_CMD_ID_RPC (0x00000002) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) + +struct nv_pmu_perf_cmd_set_object { + u8 cmd_type; + u8 pad[2]; + u8 object_type; + struct nv_pmu_allocation object; +}; + +#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \ + (offsetof(struct nv_pmu_perf_cmd_set_object, object)) + +/* RPC IDs */ +#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) + +/*! +* Command requesting execution of the perf RPC. +*/ +struct nv_pmu_perf_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_perf_cmd_rpc, request) + +/*! +* Simply a union of all specific PERF commands. Forms the general packet +* exchanged between the Kernel and PMU when sending and receiving PERF commands +* (respectively). +*/ +struct nv_pmu_perf_cmd { + union { + u8 cmd_type; + struct nv_pmu_perf_cmd_set_object set_object; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +/*! +* Defines the data structure used to invoke PMU perf RPCs. Same structure is +* used to return the result of the RPC execution. +*/ +struct nv_pmu_perf_rpc { + u8 function; + bool b_supported; + bool b_success; + flcn_status flcn_status; + union { + struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval; + struct nv_pmu_perf_rpc_vfe_load vfe_load; + } params; +}; + + +/* PERF Message-type Definitions */ +#define NV_PMU_PERF_MSG_ID_RPC (0x00000003) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) + +/*! +* Message carrying the result of the perf RPC execution. +*/ +struct nv_pmu_perf_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \ + (offsetof(struct nv_pmu_perf_msg_rpc, response)) + +/*! +* Simply a union of all specific PERF messages. Forms the general packet +* exchanged between the Kernel and PMU when sending and receiving PERF messages +* (respectively). +*/ +struct nv_pmu_perf_msg { + union { + u8 msg_type; + struct nv_pmu_perf_msg_rpc rpc; + struct nv_pmu_boardobj_msg_grp grp_set; + }; +}; + +#endif /* _GPMUIFPERF_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h new file mode 100644 index 00000000..6bad6445 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPERFVFE_H_ +#define _GPMUIFPERFVFE_H_ + +#include "gpmuifbios.h" +#include "gpmuifboardobj.h" + +#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 +#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 +#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 +#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 + +struct nv_pmu_perf_vfe_var_value { + u8 var_type; + u8 reserved[3]; + u32 var_value; +}; + +union nv_pmu_perf_vfe_equ_result { + u32 freq_m_hz; + u32 voltu_v; + u32 vf_gain; + int volt_deltau_v; +}; + +struct nv_pmu_perf_rpc_vfe_equ_eval { + u8 equ_idx; + u8 var_count; + u8 output_type; + struct nv_pmu_perf_vfe_var_value var_values[ + NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX]; + union nv_pmu_perf_vfe_equ_result result; +}; + +struct nv_pmu_perf_rpc_vfe_load { + bool b_load; +}; + +struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_perf_vfe_var_get_status_super { + struct nv_pmu_boardobj_query board_obj; +}; + +struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { + struct nv_pmu_perf_vfe_var_get_status_super super; + u32 fuse_value_integer; + u32 fuse_value_hw_integer; + u8 fuse_version; + bool b_version_check_failed; +}; + +union nv_pmu_perf_vfe_var_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_perf_vfe_var_get_status_super super; + struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var); + +struct nv_pmu_vfe_var { + struct nv_pmu_boardobj super; + u32 out_range_min; + u32 out_range_max; +}; + +struct nv_pmu_vfe_var_derived { + struct nv_pmu_vfe_var super; +}; + +struct nv_pmu_vfe_var_derived_product { + struct nv_pmu_vfe_var_derived super; + u8 var_idx0; + u8 var_idx1; +}; + +struct nv_pmu_vfe_var_derived_sum { + struct nv_pmu_vfe_var_derived super; + u8 var_idx0; + u8 var_idx1; +}; + +struct nv_pmu_vfe_var_single { + struct nv_pmu_vfe_var super; + u8 override_type; + u32 override_value; +}; + +struct nv_pmu_vfe_var_single_frequency { + struct nv_pmu_vfe_var_single super; +}; + +struct nv_pmu_vfe_var_single_sensed { + struct nv_pmu_vfe_var_single super; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_info { + u8 segment_count; + union nv_pmu_bios_vfield_register_segment segments[ + NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { + struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; + u32 fuse_val_default; + int hw_correction_scale; + int hw_correction_offset; + u8 v_field_id; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { + struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; + u8 ver_expected; + bool b_ver_check; + bool b_use_default_on_ver_check_fail; + u8 v_field_id_ver; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_override_info { + u32 fuse_val_override; + bool b_fuse_regkey_override; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse { + struct nv_pmu_vfe_var_single_sensed super; + struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; + struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; + struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; +}; + +struct nv_pmu_vfe_var_single_sensed_temp { + struct nv_pmu_vfe_var_single_sensed super; + u8 therm_channel_index; + int temp_hysteresis_positive; + int temp_hysteresis_negative; + int temp_default; +}; + +struct nv_pmu_vfe_var_single_voltage { + struct nv_pmu_vfe_var_single super; +}; + +struct nv_pmu_perf_vfe_var_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + u8 polling_periodms; +}; + +union nv_pmu_perf_vfe_var_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_vfe_var var; + struct nv_pmu_vfe_var_derived var_derived; + struct nv_pmu_vfe_var_derived_product var_derived_product; + struct nv_pmu_vfe_var_derived_sum var_derived_sum; + struct nv_pmu_vfe_var_single var_single; + struct nv_pmu_vfe_var_single_frequency var_single_frequiency; + struct nv_pmu_vfe_var_single_sensed var_single_sensed; + struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse; + struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp; + struct nv_pmu_vfe_var_single_voltage var_single_voltage; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var); + +struct nv_pmu_vfe_equ { + struct nv_pmu_boardobj super; + u8 var_idx; + u8 equ_idx_next; + u8 output_type; + u32 out_range_min; + u32 out_range_max; +}; + +struct nv_pmu_vfe_equ_compare { + struct nv_pmu_vfe_equ super; + u8 func_id; + u8 equ_idx_true; + u8 equ_idx_false; + u32 criteria; +}; + +struct nv_pmu_vfe_equ_minmax { + struct nv_pmu_vfe_equ super; + bool b_max; + u8 equ_idx0; + u8 equ_idx1; +}; + +struct nv_pmu_vfe_equ_quadratic { + struct nv_pmu_vfe_equ super; + u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT]; +}; + +struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e255 super; +}; + +union nv_pmu_perf_vfe_equ_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_vfe_equ equ; + struct nv_pmu_vfe_equ_compare equ_comapre; + struct nv_pmu_vfe_equ_minmax equ_minmax; + struct nv_pmu_vfe_equ_quadratic equ_quadratic; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ); + +#endif /* _GPMUIFPERFVFE_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h new file mode 100644 index 00000000..c480b1cf --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ +#ifndef _GPMUIFVOLT_H_ +#define _GPMUIFVOLT_H_ + +#include "ctrl/ctrlvolt.h" + +/*! +* Structure containing the number of voltage rails and the list of rail items +* @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM. +*/ +struct nv_pmu_volt_volt_rail_list { + /*! + * Number of VOLT_RAILs that require the voltage change. + */ + u8 num_rails; + /*! + * List of @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM entries. + */ + struct ctrl_perf_volt_rail_list_item rails[2]; +}; + +#endif /* _GPMUIFVOLT_H_*/ -- cgit v1.2.2