From 02190c7597d3b1a04ebcbc746b41f949ab699a18 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 31 Jan 2017 12:56:10 +0530 Subject: gpu: nvgpu: PMU interface headers reorganization Moved PMU/Falcon interface which are present in pmu_gk20a.h & pmu_common.h to new files as per feature nvgpu_gpmu_cmdif.h - Top-level header-file that defines the command/message interfaces used to communicate with PMU gpmuif_pmu.h - PMU Command/Message init interfaces gpmuif_cmn.h - Common definitions used by interfaces Jira NVGPU-19 Change-Id: Id8ea6075e4dbba7697036951dcb85487eb861710 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1296415 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h | 121 ++++++++++++++++ drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h | 215 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 85 ++++++++++++ 3 files changed, 421 insertions(+) create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h create mode 100644 drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h (limited to 'drivers/gpu/nvgpu/pmuif') diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h new file mode 100644 index 00000000..1d200129 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFCMN_H_ +#define _GPMUIFCMN_H_ + +/* + * Defines the logical queue IDs that must be used when submitting + * commands to the PMU + */ +/* write by sw, read by pmu, protected by sw mutex lock */ +#define PMU_COMMAND_QUEUE_HPQ 0 +/* write by sw, read by pmu, protected by sw mutex lock */ +#define PMU_COMMAND_QUEUE_LPQ 1 +/* read/write by sw/hw, protected by hw pmu mutex, id = 2 */ +#define PMU_COMMAND_QUEUE_BIOS 2 +/* read/write by sw/hw, protected by hw pmu mutex, id = 3 */ +#define PMU_COMMAND_QUEUE_SMI 3 +/* write by pmu, read by sw, accessed by interrupt handler, no lock */ +#define PMU_MESSAGE_QUEUE 4 +#define PMU_QUEUE_COUNT 5 + +#define PMU_IS_COMMAND_QUEUE(id) \ + ((id) < PMU_MESSAGE_QUEUE) + +#define PMU_IS_SW_COMMAND_QUEUE(id) \ + (((id) == PMU_COMMAND_QUEUE_HPQ) || \ + ((id) == PMU_COMMAND_QUEUE_LPQ)) + +#define PMU_IS_MESSAGE_QUEUE(id) \ + ((id) == PMU_MESSAGE_QUEUE) + +enum { + OFLAG_READ = 0, + OFLAG_WRITE +}; + +#define QUEUE_SET (true) +#define QUEUE_GET (false) + +#define QUEUE_ALIGNMENT (4) + +/* An enumeration containing all valid logical mutex identifiers */ +enum { + PMU_MUTEX_ID_RSVD1 = 0, + PMU_MUTEX_ID_GPUSER, + PMU_MUTEX_ID_QUEUE_BIOS, + PMU_MUTEX_ID_QUEUE_SMI, + PMU_MUTEX_ID_GPMUTEX, + PMU_MUTEX_ID_I2C, + PMU_MUTEX_ID_RMLOCK, + PMU_MUTEX_ID_MSGBOX, + PMU_MUTEX_ID_FIFO, + PMU_MUTEX_ID_PG, + PMU_MUTEX_ID_GR, + PMU_MUTEX_ID_CLK, + PMU_MUTEX_ID_RSVD6, + PMU_MUTEX_ID_RSVD7, + PMU_MUTEX_ID_RSVD8, + PMU_MUTEX_ID_RSVD9, + PMU_MUTEX_ID_INVALID +}; + +#define PMU_MUTEX_ID_IS_VALID(id) \ + ((id) < PMU_MUTEX_ID_INVALID) + +#define PMU_INVALID_MUTEX_OWNER_ID (0) + +/* + * The PMU's frame-buffer interface block has several slots/indices + * which can be bound to support DMA to various surfaces in memory + */ +enum { + PMU_DMAIDX_UCODE = 0, + PMU_DMAIDX_VIRT = 1, + PMU_DMAIDX_PHYS_VID = 2, + PMU_DMAIDX_PHYS_SYS_COH = 3, + PMU_DMAIDX_PHYS_SYS_NCOH = 4, + PMU_DMAIDX_RSVD = 5, + PMU_DMAIDX_PELPG = 6, + PMU_DMAIDX_END = 7 +}; + +/* + * Falcon PMU DMA's minimum size in bytes. + */ +#define PMU_DMA_MIN_READ_SIZE_BYTES 16 +#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 + +#define PMU_FB_COPY_RW_ALIGNMENT \ + ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \ + PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) + +/* + * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned + * data structures to issue DMA read/write operations. + */ +#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ +union name##_aligned { \ + struct name data; \ + u8 pad[ALIGN_UP(sizeof(struct name), \ + (PMU_FB_COPY_RW_ALIGNMENT))]; \ +} + +#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ +union name##_aligned { \ + union name data; \ + u8 pad[ALIGN_UP(sizeof(union name), \ + (PMU_FB_COPY_RW_ALIGNMENT))]; \ +} + +#endif /* _GPMUIFCMN_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h new file mode 100644 index 00000000..f9ffb4b1 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPMU_H_ +#define _GPMUIFPMU_H_ + +#include "gk20a/pmu_common.h" +#include "gpmuif_cmn.h" + +/* Make sure size of this structure is a multiple of 4 bytes */ +struct pmu_cmdline_args_v0 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + struct pmu_mem_v0 gc6_ctx; +}; + +struct pmu_cmdline_args_v1 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v2 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v3 { + u32 reserved; + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v4 { + u32 reserved; + u32 cpu_freq_hz; + u32 falc_trace_size; + struct falc_dma_addr dma_addr; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_desc_v0 gc6_ctx; + u8 pad; +}; + +struct pmu_cmdline_args_v5 { + u32 cpu_freq_hz; + struct flcn_mem_desc_v0 trace_buf; + u8 secure_mode; + u8 raise_priv_sec; + struct flcn_mem_desc_v0 gc6_ctx; + struct flcn_mem_desc_v0 init_data_dma_info; + u32 dummy; +}; + +/* GPU ID */ +#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 +#define PMU_SHA1_GID_SIGNATURE_SIZE 4 + +#define PMU_SHA1_GID_SIZE 16 + +struct pmu_sha1_gid { + bool valid; + u8 gid[PMU_SHA1_GID_SIZE]; +}; + +struct pmu_sha1_gid_data { + u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; + u8 gid[PMU_SHA1_GID_SIZE]; +}; + +/* PMU INIT MSG */ +enum { + PMU_INIT_MSG_TYPE_PMU_INIT = 0, +}; + +struct pmu_init_msg_pmu_v0 { + u8 msg_type; + u8 pad; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; + +struct pmu_init_msg_pmu_v1 { + u8 msg_type; + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; +struct pmu_init_msg_pmu_v2 { + u8 msg_type; + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + u8 dummy[18]; +}; + +#define PMU_QUEUE_COUNT_FOR_V4 5 +#define PMU_QUEUE_COUNT_FOR_V3 3 +#define PMU_QUEUE_HPQ_IDX_FOR_V3 0 +#define PMU_QUEUE_LPQ_IDX_FOR_V3 1 +#define PMU_QUEUE_MSG_IDX_FOR_V3 2 +struct pmu_init_msg_pmu_v3 { + u8 msg_type; + u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; + u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; + u16 queue_offset; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + + u16 os_debug_entry_point; + + u8 dummy[18]; +}; + +struct pmu_init_msg_pmu_v4 { + u8 msg_type; + u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; + u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; + u16 queue_offset; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + + u16 os_debug_entry_point; + + u8 dummy[18]; +}; + +union pmu_init_msg_pmu { + struct pmu_init_msg_pmu_v0 v0; + struct pmu_init_msg_pmu_v1 v1; + struct pmu_init_msg_pmu_v2 v2; + struct pmu_init_msg_pmu_v3 v3; + struct pmu_init_msg_pmu_v4 v4; +}; + +struct pmu_init_msg { + union { + u8 msg_type; + struct pmu_init_msg_pmu_v1 pmu_init_v1; + struct pmu_init_msg_pmu_v0 pmu_init_v0; + struct pmu_init_msg_pmu_v2 pmu_init_v2; + struct pmu_init_msg_pmu_v3 pmu_init_v3; + struct pmu_init_msg_pmu_v4 pmu_init_v4; + }; +}; + +/* robust channel (RC) messages */ +enum { + PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, +}; + +struct pmu_rc_msg_unhandled_cmd { + u8 msg_type; + u8 unit_id; +}; + +struct pmu_rc_msg { + u8 msg_type; + struct pmu_rc_msg_unhandled_cmd unhandled_cmd; +}; + +#endif /* _GPMUIFPMU_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h new file mode 100644 index 00000000..b21b3981 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPUGPMUCMDIF_H_ +#define _NVGPUGPMUCMDIF_H_ + +#include "gk20a/pmu_api.h" +#include "gk20a/pmu_common.h" +#include "gpmuif_cmn.h" +#include "gpmuif_pmu.h" +#include "gpmuifboardobj.h" +#include "gpmuifclk.h" +#include "gpmuifperf.h" +#include "gpmuifpmgr.h" +#include "gpmuifvolt.h" +#include "gpmuiftherm.h" + +struct pmu_cmd { + struct pmu_hdr hdr; + union { + struct pmu_perfmon_cmd perfmon; + struct pmu_pg_cmd pg; + struct pmu_zbc_cmd zbc; + struct pmu_acr_cmd acr; + struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; + struct nv_pmu_boardobj_cmd boardobj; + struct nv_pmu_perf_cmd perf; + struct nv_pmu_volt_cmd volt; + struct nv_pmu_clk_cmd clk; + struct nv_pmu_pmgr_cmd pmgr; + struct nv_pmu_therm_cmd therm; + } cmd; +}; + +struct pmu_msg { + struct pmu_hdr hdr; + union { + struct pmu_init_msg init; + struct pmu_perfmon_msg perfmon; + struct pmu_pg_msg pg; + struct pmu_rc_msg rc; + struct pmu_acr_msg acr; + struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; + struct nv_pmu_boardobj_msg boardobj; + struct nv_pmu_perf_msg perf; + struct nv_pmu_volt_msg volt; + struct nv_pmu_clk_msg clk; + struct nv_pmu_pmgr_msg pmgr; + struct nv_pmu_therm_msg therm; + } msg; +}; + +#define PMU_UNIT_REWIND (0x00) +#define PMU_UNIT_PG (0x03) +#define PMU_UNIT_INIT (0x07) +#define PMU_UNIT_ACR (0x0A) +#define PMU_UNIT_PERFMON_T18X (0x11) +#define PMU_UNIT_PERFMON (0x12) +#define PMU_UNIT_PERF (0x13) +#define PMU_UNIT_RC (0x1F) +#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) +#define PMU_UNIT_CLK (0x0D) +#define PMU_UNIT_THERM (0x14) +#define PMU_UNIT_PMGR (0x18) +#define PMU_UNIT_VOLT (0x0E) + +#define PMU_UNIT_END (0x23) + +#define PMU_UNIT_TEST_START (0xFE) +#define PMU_UNIT_END_SIM (0xFF) +#define PMU_UNIT_TEST_END (0xFF) + +#define PMU_UNIT_ID_IS_VALID(id) \ + (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START)) + +#endif /* _NVGPUGPMUCMDIF_H_*/ -- cgit v1.2.2