From 02190c7597d3b1a04ebcbc746b41f949ab699a18 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 31 Jan 2017 12:56:10 +0530 Subject: gpu: nvgpu: PMU interface headers reorganization Moved PMU/Falcon interface which are present in pmu_gk20a.h & pmu_common.h to new files as per feature nvgpu_gpmu_cmdif.h - Top-level header-file that defines the command/message interfaces used to communicate with PMU gpmuif_pmu.h - PMU Command/Message init interfaces gpmuif_cmn.h - Common definitions used by interfaces Jira NVGPU-19 Change-Id: Id8ea6075e4dbba7697036951dcb85487eb861710 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1296415 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h | 215 +++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h (limited to 'drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h') diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h new file mode 100644 index 00000000..f9ffb4b1 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPMU_H_ +#define _GPMUIFPMU_H_ + +#include "gk20a/pmu_common.h" +#include "gpmuif_cmn.h" + +/* Make sure size of this structure is a multiple of 4 bytes */ +struct pmu_cmdline_args_v0 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + struct pmu_mem_v0 gc6_ctx; +}; + +struct pmu_cmdline_args_v1 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v2 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v3 { + u32 reserved; + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v4 { + u32 reserved; + u32 cpu_freq_hz; + u32 falc_trace_size; + struct falc_dma_addr dma_addr; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_desc_v0 gc6_ctx; + u8 pad; +}; + +struct pmu_cmdline_args_v5 { + u32 cpu_freq_hz; + struct flcn_mem_desc_v0 trace_buf; + u8 secure_mode; + u8 raise_priv_sec; + struct flcn_mem_desc_v0 gc6_ctx; + struct flcn_mem_desc_v0 init_data_dma_info; + u32 dummy; +}; + +/* GPU ID */ +#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 +#define PMU_SHA1_GID_SIGNATURE_SIZE 4 + +#define PMU_SHA1_GID_SIZE 16 + +struct pmu_sha1_gid { + bool valid; + u8 gid[PMU_SHA1_GID_SIZE]; +}; + +struct pmu_sha1_gid_data { + u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; + u8 gid[PMU_SHA1_GID_SIZE]; +}; + +/* PMU INIT MSG */ +enum { + PMU_INIT_MSG_TYPE_PMU_INIT = 0, +}; + +struct pmu_init_msg_pmu_v0 { + u8 msg_type; + u8 pad; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; + +struct pmu_init_msg_pmu_v1 { + u8 msg_type; + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; +struct pmu_init_msg_pmu_v2 { + u8 msg_type; + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + u8 dummy[18]; +}; + +#define PMU_QUEUE_COUNT_FOR_V4 5 +#define PMU_QUEUE_COUNT_FOR_V3 3 +#define PMU_QUEUE_HPQ_IDX_FOR_V3 0 +#define PMU_QUEUE_LPQ_IDX_FOR_V3 1 +#define PMU_QUEUE_MSG_IDX_FOR_V3 2 +struct pmu_init_msg_pmu_v3 { + u8 msg_type; + u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; + u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; + u16 queue_offset; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + + u16 os_debug_entry_point; + + u8 dummy[18]; +}; + +struct pmu_init_msg_pmu_v4 { + u8 msg_type; + u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; + u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; + u16 queue_offset; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + + u16 os_debug_entry_point; + + u8 dummy[18]; +}; + +union pmu_init_msg_pmu { + struct pmu_init_msg_pmu_v0 v0; + struct pmu_init_msg_pmu_v1 v1; + struct pmu_init_msg_pmu_v2 v2; + struct pmu_init_msg_pmu_v3 v3; + struct pmu_init_msg_pmu_v4 v4; +}; + +struct pmu_init_msg { + union { + u8 msg_type; + struct pmu_init_msg_pmu_v1 pmu_init_v1; + struct pmu_init_msg_pmu_v0 pmu_init_v0; + struct pmu_init_msg_pmu_v2 pmu_init_v2; + struct pmu_init_msg_pmu_v3 pmu_init_v3; + struct pmu_init_msg_pmu_v4 pmu_init_v4; + }; +}; + +/* robust channel (RC) messages */ +enum { + PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, +}; + +struct pmu_rc_msg_unhandled_cmd { + u8 msg_type; + u8 unit_id; +}; + +struct pmu_rc_msg { + u8 msg_type; + struct pmu_rc_msg_unhandled_cmd unhandled_cmd; +}; + +#endif /* _GPMUIFPMU_H_*/ -- cgit v1.2.2