From c6cfb12d91accc759ed80985573014df89d9cdaa Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Tue, 11 Sep 2018 10:38:54 +0530 Subject: gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1809757 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/pmgr/pwrpolicy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.h') diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h index 868bc2cb..74f4937d 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h @@ -29,7 +29,7 @@ #include "boardobj/boardobj.h" #include "ctrl/ctrlpmgr.h" -#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4 +#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U enum pwr_policy_limit_id { PWR_POLICY_LIMIT_ID_MIN = 0x00000000, -- cgit v1.2.2