From 7f8226887c28267d3c2351692d4429ead1e17695 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 29 Aug 2018 15:46:12 -0400 Subject: gpu: nvgpu: cleanup return types for MISRA 10.3 This is a big cleanup of return types across a number of modules in the nvgpu driver. Many functions were returning u32 but using negative return codes. This is a MISRA 10.3 violation by assigning signed values to a u32. JIRA NVGPU-647 Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1810743 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/pmgr/pmgrpmu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/pmgr/pmgrpmu.h') diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h index 3cb9eecb..a576f384 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h @@ -1,7 +1,7 @@ /* * general power device control structures & definitions * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,7 +28,7 @@ #include "pwrdev.h" #include "pwrmonitor.h" -u32 pmgr_send_pmgr_tables_to_pmu(struct gk20a *g); +int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g); u32 pmgr_pmu_pwr_devices_query_blocking( struct gk20a *g, -- cgit v1.2.2