From c6cfb12d91accc759ed80985573014df89d9cdaa Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Tue, 11 Sep 2018 10:38:54 +0530 Subject: gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1809757 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/pmgr/pmgrpmu.c') diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index 411550be..b6947f20 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c @@ -52,7 +52,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_SET_OBJECT) { if ((msg->msg.pmgr.set_object.b_success != 1) || - (msg->msg.pmgr.set_object.flcnstatus != 0) ) { + (msg->msg.pmgr.set_object.flcnstatus != 0U)) { nvgpu_err(g, "pmgr msg failed %x %x %x %x", msg->msg.pmgr.set_object.msg_type, msg->msg.pmgr.set_object.b_success, @@ -62,7 +62,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, } } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_QUERY) { if ((msg->msg.pmgr.query.b_success != 1) || - (msg->msg.pmgr.query.flcnstatus != 0) ) { + (msg->msg.pmgr.query.flcnstatus != 0U)) { nvgpu_err(g, "pmgr msg failed %x %x %x %x", msg->msg.pmgr.query.msg_type, msg->msg.pmgr.query.b_success, @@ -72,7 +72,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, } } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_LOAD) { if ((msg->msg.pmgr.query.b_success != 1) || - (msg->msg.pmgr.query.flcnstatus != 0) ) { + (msg->msg.pmgr.query.flcnstatus != 0U)) { nvgpu_err(g, "pmgr msg failed %x %x %x", msg->msg.pmgr.load.msg_type, msg->msg.pmgr.load.b_success, @@ -133,7 +133,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g, gk20a_get_gr_idle_timeout(g), &handlerparams.success, 1); - if (handlerparams.success == 0) { + if (handlerparams.success == 0U) { nvgpu_err(g, "could not process cmd"); status = -ETIMEDOUT; goto exit; @@ -431,7 +431,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking( gk20a_get_gr_idle_timeout(g), &handlerparams.success, 1); - if (handlerparams.success == 0) { + if (handlerparams.success == 0U) { nvgpu_err(g, "could not process cmd"); status = -ETIMEDOUT; goto exit; @@ -475,7 +475,7 @@ static u32 pmgr_pmu_load_blocking(struct gk20a *g) gk20a_get_gr_idle_timeout(g), &handlerparams.success, 1); - if (handlerparams.success == 0) { + if (handlerparams.success == 0U) { nvgpu_err(g, "could not process cmd"); status = -ETIMEDOUT; goto exit; -- cgit v1.2.2