From 7f8226887c28267d3c2351692d4429ead1e17695 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 29 Aug 2018 15:46:12 -0400 Subject: gpu: nvgpu: cleanup return types for MISRA 10.3 This is a big cleanup of return types across a number of modules in the nvgpu driver. Many functions were returning u32 but using negative return codes. This is a MISRA 10.3 violation by assigning signed values to a u32. JIRA NVGPU-647 Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1810743 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/pmgr/pmgrpmu.c') diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index 3398e8df..69c43a01 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -175,11 +175,11 @@ static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g) return status; } -static u32 pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) +static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) { struct nv_pmu_pmgr_pwr_device_desc_table *pwr_desc_table; struct nv_pmu_pmgr_pwr_device_desc_table_header *ppwr_desc_header; - u32 status = 0; + int status = 0; /* Set the BA-device-independent HW information */ pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table)); @@ -221,13 +221,13 @@ exit: return status; } -static u32 pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) +static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) { struct nv_pmu_pmgr_pwr_monitor_pack *pwr_monitor_pack = NULL; struct nv_pmu_pmgr_pwr_channel_header *pwr_channel_hdr; struct nv_pmu_pmgr_pwr_chrelationship_header *pwr_chrelationship_header; u32 max_dmem_size; - u32 status = 0; + int status = 0; pwr_monitor_pack = nvgpu_kzalloc(g, sizeof(*pwr_monitor_pack)); if (!pwr_monitor_pack) @@ -290,11 +290,11 @@ exit: return status; } -static u32 pmgr_send_pwr_policy_to_pmu(struct gk20a *g) +static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g) { struct nv_pmu_pmgr_pwr_policy_pack *ppwrpack = NULL; struct pwr_policy *ppolicy = NULL; - u32 status = 0; + int status = 0; u8 indx; u32 max_dmem_size; @@ -479,9 +479,9 @@ exit: return status; } -u32 pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) +int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) { - u32 status = 0; + int status = 0; status = pmgr_send_i2c_device_topology_to_pmu(g); -- cgit v1.2.2