From 74ceef1230f414956aceaa027580c6f71fe42153 Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Wed, 25 Apr 2018 13:04:49 +0530 Subject: gpu:nvgpu: Update vfe_load for GV100 Add gops to choose vfe_load between GP and GV. Bug 200399373 Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b Signed-off-by: Vaikundanathan S Reviewed-on: https://git-master.nvidia.com/r/1702143 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/perf/perf.c | 15 +++++++++++++++ drivers/gpu/nvgpu/perf/perf.h | 1 + 2 files changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/perf') diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index bf63e1ea..900496fd 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c @@ -65,6 +65,21 @@ static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg) return 0; } +u32 perf_pmu_vfe_load_gv10x(struct gk20a *g) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct nv_pmu_rpc_struct_perf_load rpc; + u32 status = 0; + + memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); + PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); + if (status) { + nvgpu_err(g, "Failed to execute RPC status=0x%x", + status); + } + return status; +} + u32 perf_pmu_vfe_load(struct gk20a *g) { struct pmu_cmd cmd; diff --git a/drivers/gpu/nvgpu/perf/perf.h b/drivers/gpu/nvgpu/perf/perf.h index c3708f61..180efb2c 100644 --- a/drivers/gpu/nvgpu/perf/perf.h +++ b/drivers/gpu/nvgpu/perf/perf.h @@ -74,5 +74,6 @@ struct perf_pmupstate { }; u32 perf_pmu_vfe_load(struct gk20a *g); +u32 perf_pmu_vfe_load_gv10x(struct gk20a *g); #endif -- cgit v1.2.2