From ae809fddbe90bcec0d48e1213fa36cc5ba76550d Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Tue, 28 Aug 2018 11:58:25 +0530 Subject: gpu:nvgpu: Add GV10x perf event In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/perf/perf.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/perf/perf.h') diff --git a/drivers/gpu/nvgpu/perf/perf.h b/drivers/gpu/nvgpu/perf/perf.h index 180efb2c..17a9b0e1 100644 --- a/drivers/gpu/nvgpu/perf/perf.h +++ b/drivers/gpu/nvgpu/perf/perf.h @@ -65,15 +65,21 @@ struct gk20a; +struct nvgpu_vfe_invalidate { + bool state_change; + struct nvgpu_cond wq; + struct nvgpu_thread state_task; +}; + struct perf_pmupstate { struct vfe_vars vfe_varobjs; struct vfe_equs vfe_equobjs; struct pstates pstatesobjs; struct obj_volt volt; struct obj_lwpr lpwr; + struct nvgpu_vfe_invalidate vfe_init; }; u32 perf_pmu_vfe_load(struct gk20a *g); -u32 perf_pmu_vfe_load_gv10x(struct gk20a *g); #endif -- cgit v1.2.2