From a6108a4b0ed52c7a8fa58d9815d0b373be8305bf Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Tue, 28 Aug 2018 18:13:28 -0700 Subject: gpu: nvgpu: Fix GM20b GPCPLL debugfs node GM20B GPCPLL registers are accessed via sys address space with the exception of the last dvfs2 register that can be accessed only through bcast address. However, in debugfs loop dvfs2 sys address should be used as loop terminator; otherwise, loop body is never executed, and GPCPLL registers debugfs node is broken. Fixed it in this commit. Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0 Signed-off-by: Alex Frid Reviewed-on: https://git-master.nvidia.com/r/1808784 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/os') diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c b/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c index f514d2c8..52eea83f 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c +++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c @@ -108,10 +108,14 @@ static int pll_reg_raw_show(struct seq_file *s, void *data) seq_puts(s, "GPCPLL REGISTERS:\n"); for (reg = d.trim_sys_gpcpll_cfg_reg; - reg <= d.trim_sys_gpcpll_dvfs2_reg; + reg < d.trim_sys_gpcpll_dvfs2_reg; reg += sizeof(u32)) seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); + reg = d.trim_bcast_gpcpll_dvfs2_reg; + if (reg) + seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); + seq_puts(s, "\nGPC CLK OUT REGISTERS:\n"); seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg, -- cgit v1.2.2