From e0dbf3a784f6cb1a6e1c41a23123b19ec73b8708 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 18 Jan 2018 11:44:47 +0530 Subject: gpu: nvgpu: gv11b: Enable perfmon. t19x PMU ucode uses RPC mechanism for PERFMON commands. - Declared "pmu_init_perfmon", "pmu_perfmon_start_sampling", "pmu_perfmon_stop_sampling" and "pmu_perfmon_get_samples" in pmu ops to differenciate for chips using RPC & legacy cmd/msg mechanism. - Defined and used PERFMON RPC commands for t19x - INIT - START - STOP - QUERY - Adds RPC handler for PERFMON RPC commands. - For guerying GPU utilization/load, we need to send PERFMON_QUERY RPC command for gv11b. - Enables perfmon for gv11b. Bug 2039013 Change-Id: Ic32326f81d48f11bc772afb8fee2dee6e427a699 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1614114 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 7 ++ .../gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | 84 ++++++++++++++++++++++ 2 files changed, 91 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index cd7e1879..5e9983b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -329,6 +329,8 @@ struct nvgpu_pmu { u32 *ucode_image; bool pmu_ready; + u32 perfmon_query; + u32 zbc_save_done; u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; @@ -362,6 +364,7 @@ struct nvgpu_pmu { u32 sample_buffer; u32 load_shadow; u32 load_avg; + u32 load; struct nvgpu_mutex isr_mutex; bool isr_enabled; @@ -432,8 +435,12 @@ int nvgpu_pmu_process_message(struct nvgpu_pmu *pmu); int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu); int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu); int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu); +int nvgpu_pmu_perfmon_start_sampling_rpc(struct nvgpu_pmu *pmu); +int nvgpu_pmu_perfmon_stop_sampling_rpc(struct nvgpu_pmu *pmu); +int nvgpu_pmu_perfmon_get_samples_rpc(struct nvgpu_pmu *pmu); int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu, struct pmu_perfmon_msg *msg); +int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu); int nvgpu_pmu_load_norm(struct gk20a *g, u32 *load); int nvgpu_pmu_load_update(struct gk20a *g); void nvgpu_pmu_reset_load_counters(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h index f8c15324..bcf4c8b6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h @@ -32,6 +32,8 @@ #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) +#define NV_PMU_PERFMON_MAX_COUNTERS 10 + enum pmu_perfmon_cmd_start_fields { COUNTER_ALLOC }; @@ -61,6 +63,15 @@ struct pmu_perfmon_counter_v2 { u32 scale; }; +struct pmu_perfmon_counter_v3 { + u8 index; + u8 group_id; + u16 flags; + u16 upper_threshold; /* units of 0.01% */ + u16 lower_threshold; /* units of 0.01% */ + u32 scale; +}; + struct pmu_perfmon_cmd_start_v3 { u8 cmd_type; u8 group_id; @@ -184,4 +195,77 @@ struct pmu_perfmon_msg { }; }; +/* PFERMON RPC interface*/ +/* + * RPC calls serviced by PERFMON unit. + */ +#define NV_PMU_RPC_ID_PERFMON_T18X_INIT 0x00 +#define NV_PMU_RPC_ID_PERFMON_T18X_DEINIT 0x01 +#define NV_PMU_RPC_ID_PERFMON_T18X_START 0x02 +#define NV_PMU_RPC_ID_PERFMON_T18X_STOP 0x03 +#define NV_PMU_RPC_ID_PERFMON_T18X_QUERY 0x04 +#define NV_PMU_RPC_ID_PERFMON_T18X__COUNT 0x05 + +/* + * structure that holds data used to + * execute Perfmon INIT RPC. + * hdr - RPC header + * sample_periodus - Desired period in between samples. + * to_decrease_count - Consecutive samples before decrease event. + * base_counter_id - Index of the base counter. + * samples_in_moving_avg - Number of values in moving average. + * num_counters - Num of counters PMU should use. + * counter - Counters. + */ +struct nv_pmu_rpc_struct_perfmon_init { + struct nv_pmu_rpc_header hdr; + u32 sample_periodus; + u8 to_decrease_count; + u8 base_counter_id; + u8 samples_in_moving_avg; + u8 num_counters; + struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; + u32 scratch[1]; +}; + +/* + * structure that holds data used to + * execute Perfmon START RPC. + * hdr - RPC header + * group_id - NV group ID + * state_id - NV state ID + * flags - PMU_PERFON flags + * counters - Counters. + */ +struct nv_pmu_rpc_struct_perfmon_start { + struct nv_pmu_rpc_header hdr; + u8 group_id; + u8 state_id; + u8 flags; + struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; + u32 scratch[1]; +}; + +/* + * structure that holds data used to + * execute Perfmon STOP RPC. + * hdr - RPC header + */ +struct nv_pmu_rpc_struct_perfmon_stop { + struct nv_pmu_rpc_header hdr; + u32 scratch[1]; +}; + +/* + * structure that holds data used to + * execute QUERY RPC. + * hdr - RPC header + * sample_buffer - Output buffer from pmu containing utilization samples. + */ +struct nv_pmu_rpc_struct_perfmon_query { + struct nv_pmu_rpc_header hdr; + u16 sample_buffer[NV_PMU_PERFMON_MAX_COUNTERS]; + u32 scratch[1]; +}; + #endif /* _GPMUIFPERFMON_H_ */ -- cgit v1.2.2