From d3f96dfa96a8aafe6f5035e2ed24425141e4202e Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 14 Feb 2018 14:31:01 +0530 Subject: gpu: nvgpu: gv10x volt rail boardobj changes - Created volt ops under pmu_ver to support volt_set_voltage, volt_get_voltage & volt_send_load_cmd_to_pmu. - Renamed volt load, set_voltage & get_voltage gp10x method names. - Added new volt load, set_voltage & get_voltage methods for gv10x using RPC & added code to handle ack in pmu_rpc_handler() along with struct rail_list changes. - Updated volt ops of gp106 & gv100 to point to respective methods. - Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to "struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail" made changes to update members as needed. - Added member volt_scale_exp_pwr_equ_idx to "struct vbios_voltage_rail_table_1x_entry" to read value from VBIOS table & update rail boardobj set interface. - Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*" - Define struct's volt load, set_voltage & get_voltage to execute volt RPC. Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1659728 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/bios.h | 2 + drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 61 +++++++++++++++++++++- 2 files changed, 61 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index fb0a313f..75f8da35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -725,6 +725,7 @@ struct vbios_voltage_rail_table_1x_header { #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000C struct vbios_voltage_rail_table_1x_entry { u32 boot_voltage_uv; @@ -735,6 +736,7 @@ struct vbios_voltage_rail_table_1x_entry { u8 boot_volt_vfe_equ_idx; u8 vmin_limit_vfe_equ_idx; u8 volt_margin_limit_vfe_equ_idx; + u8 volt_scale_exp_pwr_equ_idx; } __packed; /* Voltage Device Table */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index c3d540cc..3b286139 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -49,6 +49,8 @@ struct nv_pmu_volt_volt_rail_boardobj_set { u8 volt_margin_limit_vfe_equ_idx; u8 pwr_equ_idx; u8 volt_dev_idx_default; + u8 volt_dev_idx_ipc_vmin; + u8 volt_scale_exp_pwr_equ_idx; struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; }; @@ -101,7 +103,6 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; }; @@ -332,4 +333,60 @@ struct nv_pmu_volt_volt_rail_list { rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; }; +struct nv_pmu_volt_volt_rail_list_V1 { + u8 num_rails; + struct ctrl_volt_volt_rail_list_item_v1 + rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; +}; + +/* VOLT RPC */ +#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00 +#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01 +#define NV_PMU_RPC_ID_VOLT_LOAD 0x02 +#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03 +#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04 +#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05 +#define NV_PMU_RPC_ID_VOLT__COUNT 0x06 + +/* + * Defines the structure that holds data + * used to execute LOAD RPC. + */ +struct nv_pmu_rpc_struct_volt_load { + /*[IN/OUT] Must be first field in RPC structure */ + struct nv_pmu_rpc_header hdr; + u32 scratch[1]; +}; + +/* + * Defines the structure that holds data + * used to execute VOLT_SET_VOLTAGE RPC. + */ +struct nv_pmu_rpc_struct_volt_volt_set_voltage { + /*[IN/OUT] Must be first field in RPC structure */ + struct nv_pmu_rpc_header hdr; + /*[IN] ID of the client that wants to set the voltage */ + u8 client_id; + /* + * [IN] The list containing target voltage and + * noise-unaware Vmin value for the VOLT_RAILs. + */ + struct ctrl_volt_volt_rail_list_v1 rail_list; + u32 scratch[1]; +}; + +/* + * Defines the structure that holds data + * used to execute VOLT_RAIL_GET_VOLTAGE RPC. + */ +struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage { + /*[IN/OUT] Must be first field in RPC structure */ + struct nv_pmu_rpc_header hdr; + /* [OUT] Current voltage in uv */ + u32 voltage_uv; + /* [IN] Voltage Rail Table Index */ + u8 rail_idx; + u32 scratch[1]; +}; + #endif /* _GPMUIFVOLT_H_*/ -- cgit v1.2.2