From cc4b9f540f66abc9f60cf9f8e2217ff17349bc77 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 13 Feb 2018 14:37:18 +0530 Subject: gpu: nvgpu: PMU super surface support - Added ops "pmu.alloc_super_surface" to create memory space for pmu super surface - Defined method nvgpu_pmu_sysmem_surface_alloc() to allocate pmu super surface memory & assigned to "pmu.alloc_super_surface" for gv100 - "pmu.alloc_super_surface" set to NULL for gp106 - Memory space of size "struct nv_pmu_super_surface" is allocated during pmu sw init setup if "pmu.alloc_super_surface" is not NULL & free if error occur. - Added ops "pmu_ver.config_pmu_cmdline_args_super_surface" to describe PMU super surface details to PMU ucode as part of pmu command line args command if "pmu.alloc_super_surface" is not NULL. - Updated pmu_cmdline_args_v6 to include member "struct flcn_mem_desc_v0 super_surface" - Free allocated memory for PMU super surface in nvgpu_remove_pmu_support() method - Added "struct nvgpu_mem super_surface_buf" to "nvgpu_pmu" struct - Created header file "gpmu_super_surf_if.h" to include interface about pmu super surface, added "struct nv_pmu_super_surface" to hold super surface members along with rsvd[x] dummy space to sync members offset with PMU super surface members. Change-Id: I2b28912bf4d86a8cc72884e3b023f21c73fb3503 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1656571 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 4 ++ .../nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h | 77 ++++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 4 +- .../nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 1 + 4 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 5e34abe6..76a54fa1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -306,6 +306,8 @@ struct nvgpu_pmu { /* TBD: remove this if ZBC seq is fixed */ struct nvgpu_mem seq_buf; struct nvgpu_mem trace_buf; + struct nvgpu_mem super_surface_buf; + bool buf_loaded; struct pmu_sha1_gid gid_info; @@ -449,6 +451,8 @@ int nvgpu_init_pmu_support(struct gk20a *g); int nvgpu_pmu_destroy(struct gk20a *g); int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu, struct pmu_msg *msg); +int nvgpu_pmu_super_surface_alloc(struct gk20a *g, + struct nvgpu_mem *mem_surface, u32 size); void nvgpu_pmu_state_change(struct gk20a *g, u32 pmu_state, bool post_change_event); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h new file mode 100644 index 00000000..cf39658f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __GPMU_SUPER_SURF_IF_H__ +#define __GPMU_SUPER_SURF_IF_H__ + +struct nv_pmu_super_surface_hdr { + u32 memberMask; + u16 dmemBufferSizeMax; +}; + +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr, + sizeof(struct nv_pmu_super_surface_hdr)); + +/* + * Global Super Surface structure for combined INIT data required by PMU. + * NOTE: Any new substructures or entries must be aligned. + */ +struct nv_pmu_super_surface { + union nv_pmu_super_surface_hdr_aligned hdr; + + struct { + struct nv_pmu_volt_volt_device_boardobj_grp_set volt_device_grp_set; + struct nv_pmu_volt_volt_policy_boardobj_grp_set volt_policy_grp_set; + struct nv_pmu_volt_volt_rail_boardobj_grp_set volt_rail_grp_set; + + struct nv_pmu_volt_volt_policy_boardobj_grp_get_status volt_policy_grp_get_status; + struct nv_pmu_volt_volt_rail_boardobj_grp_get_status volt_rail_grp_get_status; + struct nv_pmu_volt_volt_device_boardobj_grp_get_status volt_device_grp_get_status; + } volt; + struct { + struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set; + struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set; + struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set; + struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set; + struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set; + struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set; + + struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status; + struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status; + struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status; + u8 clk_rsvd[0x4660]; + } clk; + struct { + struct nv_pmu_perf_vfe_equ_boardobj_grp_set vfe_equ_grp_set; + struct nv_pmu_perf_vfe_var_boardobj_grp_set vfe_var_grp_set; + + struct nv_pmu_perf_vfe_var_boardobj_grp_get_status vfe_var_grp_get_status; + u8 perf_rsvd[0x40790]; + u8 perfcf_rsvd[0x1eb0]; + } perf; + struct { + struct nv_pmu_therm_therm_channel_boardobj_grp_set therm_channel_grp_set; + struct nv_pmu_therm_therm_device_boardobj_grp_set therm_device_grp_set; + u8 therm_rsvd[0x1460]; + } therm; +}; + +#endif /* __GPMU_SUPER_SURF_IF_H__ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 5f718dc6..2dd511de 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h @@ -66,8 +66,8 @@ struct pmu_cmdline_args_v6 { u8 raise_priv_sec; struct flcn_mem_desc_v0 gc6_ctx; struct flcn_mem_desc_v0 gc6_bsod_ctx; - struct flcn_mem_desc_v0 init_data_dma_info; - u32 dummy; + struct flcn_mem_desc_v0 super_surface; + u32 flags; }; /* GPU ID */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h index 208644d7..1a05ec29 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h @@ -38,6 +38,7 @@ #include "gpmuiftherm.h" #include "gpmuifthermsensor.h" #include "gpmuifseq.h" +#include "gpmu_super_surf_if.h" /* * Command requesting execution of the RPC (Remote Procedure Call) -- cgit v1.2.2