From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 217 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 133 + .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 81 + .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 445 +++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 1485 +++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 517 +++ .../nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 181 + .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 137 + .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 1477 ++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 3509 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 593 ++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 245 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 633 ++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 205 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 57 + .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 145 + .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 69 + .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 161 + .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 825 +++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 765 +++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 53 + .../nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 109 + .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 221 ++ .../include/nvgpu/hw/gv11b/hw_usermode_gv11b.h | 89 + 24 files changed, 12352 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h new file mode 100644 index 00000000..66571ae7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gv11b_h_ +#define _hw_bus_gv11b_h_ + +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h new file mode 100644 index 00000000..618c4806 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gv11b_h_ +#define _hw_ccsr_gv11b_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00000200; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00000200; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) +{ + return 0x400000; +} +static inline u32 ccsr_channel_eng_faulted_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 ccsr_channel_eng_faulted_reset_f(void) +{ + return 0x800000; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h new file mode 100644 index 00000000..9f279207 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gv11b_h_ +#define _hw_ce_gv11b_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h new file mode 100644 index 00000000..228bf5f2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gv11b_h_ +#define _hw_ctxsw_prog_gv11b_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) +{ + return 0x00000011; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) +{ + return 0x00000012; +} +static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) +{ + return 0x00000021; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7 << 0; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) +{ + return 0x00000060; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) +{ + return 0x00000064; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) +{ + return 0x00000070; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) +{ + return 0x00000074; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) +{ + return 0x00000078; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) +{ + return 0x0000007c; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) +{ + return 0x000000b8; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) +{ + return 0x000000bc; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) +{ + return 0x000000c0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) +{ + return 0x000000c4; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) +{ + return 0x000000c8; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) +{ + return 0x000000cc; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) +{ + return 0x000000e0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) +{ + return 0x000000e4; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h new file mode 100644 index 00000000..d2f22afa --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -0,0 +1,1485 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gv11b_h_ +#define _hw_fb_gv11b_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10; +} +static inline u32 fb_niso_intr_r(void) +{ + return 0x00100a20; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_r(u32 i) +{ + return 0x00100a24 + i*4; +} +static inline u32 fb_niso_intr_en__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_set_r(u32 i) +{ + return 0x00100a2c + i*4; +} +static inline u32 fb_niso_intr_en_set__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_r(u32 i) +{ + return 0x00100a34 + i*4; +} +static inline u32 fb_niso_intr_en_clr__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) +{ + return 0x00000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) +{ + return 0x00100e24 + i*20; +} +static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) +{ + return (r >> 1) & 0x3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x6; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) +{ + return 0x00100e28 + i*20; +} +static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_buffer_get_r(u32 i) +{ + return 0x00100e2c + i*20; +} +static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_put_r(u32 i) +{ + return 0x00100e30 + i*20; +} +static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_size_r(u32 i) +{ + return 0x00100e34 + i*20; +} +static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) +{ + return 0x20000000; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_addr_lo_r(void) +{ + return 0x00100e4c; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_addr_hi_r(void) +{ + return 0x00100e50; +} +static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_inst_lo_r(void) +{ + return 0x00100e54; +} +static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) +{ + return (r >> 10) & 0x3; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_inst_hi_r(void) +{ + return 0x00100e58; +} +static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_info_r(void) +{ + return 0x00100e5c; +} +static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fb_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 fb_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_info_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_r(void) +{ + return 0x00100e60; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_replayable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fb_mmu_fault_status_replayable_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_set_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) +{ + return (r >> 9) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) +{ + return 0x200; +} +static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) +{ + return 0x400; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) +{ + return 0x1000; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) +{ + return 0x2000; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) +{ + return (r >> 14) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) +{ + return 0x4000; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) +{ + return 0x8000; +} +static inline u32 fb_mmu_fault_status_busy_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_status_busy_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_status_busy_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_busy_true_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_status_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_status_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_valid_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_status_valid_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_clear_f(void) +{ + return 0x80000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h new file mode 100644 index 00000000..d68c823a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gv11b_h_ +#define _hw_fifo_gv11b_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_userd_writeback_r(void) +{ + return 0x0000225c; +} +static inline u32 fifo_userd_writeback_timer_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_userd_writeback_timer_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_userd_writeback_timer_shorter_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_userd_writeback_timer_100us_v(void) +{ + return 0x00000064; +} +static inline u32 fifo_userd_writeback_timescale_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 fifo_userd_writeback_timescale_0_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) +{ + return 0x0000000a; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_hub_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_error_sched_disable_r(void) +{ + return 0x0000262c; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_cfg0_r(void) +{ + return 0x00002004; +} +static inline u32 fifo_cfg0_num_pbdma_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) +{ + return (r >> 16) & 0xff; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h new file mode 100644 index 00000000..380f8824 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gv11b_h_ +#define _hw_flush_gv11b_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h new file mode 100644 index 00000000..280a048a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gv11b_h_ +#define _hw_fuse_gv11b_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0xff << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h new file mode 100644 index 00000000..1c523f87 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -0,0 +1,1477 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gv11b_h_ +#define _hw_gmmu_gv11b_h_ + +static inline u32 gmmu_new_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_vol_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_vol_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_new_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_read_only_true_f(void) +{ + return 0x40; +} +static inline u32 gmmu_new_pte_comptagline_f(u32 v) +{ + return (v & 0x3ffff) << 4; +} +static inline u32 gmmu_new_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_kind_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gmmu_new_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} +static inline u32 gmmu_pte_kind_z16_4cz_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) +{ + return 0x0000000d; +} +static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) +{ + return 0x0000000e; +} +static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) +{ + return 0x0000000f; +} +static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +static inline u32 gmmu_fault_buf_size_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) +{ + return (r >> 8) & 0x3; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) +{ + return 0; +} +static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) +{ + return 1; +} +static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) +{ + return 2; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) +{ + return 2; +} +static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) +{ + return 3; +} +static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) +{ + return 4; +} +static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) +{ + return 5; +} +static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 gmmu_fault_buf_entry_engine_id_w(void) +{ + return 6; +} +static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gmmu_fault_buf_entry_fault_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) +{ + return 0x80; +} +static inline u32 gmmu_fault_buf_entry_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 gmmu_fault_buf_entry_client_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 gmmu_fault_buf_entry_access_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) +{ + return 0x20000000; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) +{ + return 0x40000000; +} +static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_valid_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_valid_true_f(void) +{ + return 0x80000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h new file mode 100644 index 00000000..656597ba --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -0,0 +1,3509 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gv11b_h_ +#define _hw_gr_gv11b_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x0050433c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419b3c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x00504358; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_address_veid_f(u32 v) +{ + return (v & 0x3f) << 20; +} +static inline u32 gr_pipe_bundle_address_veid_w(void) +{ + return 0; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) +{ + return 0x00419ea8; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) +{ + return 0x00419eac; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x1800; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fe_tpc_fs_r(u32 i) +{ + return 0x0040a200 + i*4; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} +static inline u32 gr_rstr2d_gpc_map_r(u32 i) +{ + return 0x0040780c + i*4; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x00000380; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00000302; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) +{ + return 0x00405830; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) +{ + return 0x0040585c; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000030; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000200; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0x3ff) << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0x3ff << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 10) & 0x3ff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504608; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x00504330; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00001100; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419e04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000030; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x30; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x005001dc; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x00000170; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x005001d8; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x004181e4; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00418100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0041814c; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) +{ + return 0x0041815c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) +{ + return 0x00418198; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_gpc_map_r(u32 i) +{ + return 0x00418b08 + i*4; +} +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +{ + return (v & 0x1f) << 25; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +{ + return 0x00418980 + i*4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00419f28; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x00419f2c; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) +{ + return 0x00419d0c; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) +{ + return 0x0041ac94; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) +{ + return 0x00504704; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) +{ + return 0x00504708; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) +{ + return 0x00504710; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) +{ + return 0x00504718; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) +{ + return 0x00419f10; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) +{ + return 0x00504700; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) +{ + return 0x00419f34; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) +{ + return 0x00504730; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) +{ + return 0xf << 24; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) +{ + return 0x00504738; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x005043a0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419ba0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x005043b0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419bb0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +{ + return 0x0041bf00 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) +{ + return 0x0041bfb0 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) +{ + return 0x00000005; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) +{ + return 0x00419f04; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419bd8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419ba4; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0x1ff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h new file mode 100644 index 00000000..6968c699 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gv11b_h_ +#define _hw_ltc_gv11b_h_ + +static inline u32 ltc_pltcg_base_v(void) +{ + return 0x00140000; +} +static inline u32 ltc_pltcg_extent_v(void) +{ + return 0x0017ffff; +} +static inline u32 ltc_ltc0_ltss_v(void) +{ + return 0x00140200; +} +static inline u32 ltc_ltc0_lts0_v(void) +{ + return 0x00140400; +} +static inline u32 ltc_ltcs_ltss_v(void) +{ + return 0x0017e200; +} +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0003ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) +{ + return 0x0017e204; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) +{ + return 8; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_intr_r(void) +{ + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h new file mode 100644 index 00000000..98bec43a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gv11b_h_ +#define _hw_mc_gv11b_h_ + +static inline u32 mc_boot_0_r(void) +{ + return 0x00000000; +} +static inline u32 mc_boot_0_architecture_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 mc_boot_0_implementation_v(u32 r) +{ + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; +} +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_en_r(u32 i) +{ + return 0x00000140 + i*4; +} +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_priv_ring_enabled_f(void) +{ + return 0x20; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h new file mode 100644 index 00000000..c4d3a631 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gv11b_h_ +#define _hw_pbdma_gv11b_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x00000003; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_config_r(u32 i) +{ + return 0x000400f4 + i*8192; +} +static inline u32 pbdma_config_l2_evict_first_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_l2_evict_normal_f(void) +{ + return 0x1; +} +static inline u32 pbdma_config_l2_evict_last_f(void) +{ + return 0x2; +} +static inline u32 pbdma_config_ce_split_enable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_ce_split_disable_f(void) +{ + return 0x10; +} +static inline u32 pbdma_config_auth_level_non_privileged_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_auth_level_privileged_f(void) +{ + return 0x100; +} +static inline u32 pbdma_config_userd_writeback_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_userd_writeback_enable_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_allowed_syncpoints_r(u32 i) +{ + return 0x000400e8 + i*8192; +} +static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) +{ + return (v & 0x7fff) << 16; +} +static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) +{ + return (r >> 16) & 0x7fff; +} +static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) +{ + return (v & 0x7fff) << 0; +} +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_target_eng_ctx_valid_true_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_target_eng_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_ce_ctx_valid_true_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_target_ce_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) +{ + return 0x3000000; +} +static inline u32 pbdma_target_should_send_tsg_event_true_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_target_should_send_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_r(u32 i) +{ + return 0x000400fc + i*8192; +} +static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) +{ + return 0x1; +} +static inline u32 pbdma_set_channel_info_veid_f(u32 v) +{ + return (v & 0x3f) << 8; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h new file mode 100644 index 00000000..836c014b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gv11b_h_ +#define _hw_perf_gv11b_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x0024a000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x0024a070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x0024a074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x0024a078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x0024a07c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x0024a084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x0024a088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x0024a0a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h new file mode 100644 index 00000000..da2d4d2e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pram_gv11b_h_ +#define _hw_pram_gv11b_h_ + +static inline u32 pram_data032_r(u32 i) +{ + return 0x00700000 + i*4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h new file mode 100644 index 00000000..835366c1 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gv11b_h_ +#define _hw_pri_ringmaster_gv11b_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h new file mode 100644 index 00000000..e192bd13 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gv11b_h_ +#define _hw_pri_ringstation_sys_gv11b_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h new file mode 100644 index 00000000..4e30447c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gv11b_h_ +#define _hw_proj_gv11b_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_fbpa_stride_v(void) +{ + return 0x00004000; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_engines_v(void) +{ + return 0x00000004; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x00000003; +} +static inline u32 proj_litter_num_subctx_v(void) +{ + return 0x00000040; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_fbpas_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h new file mode 100644 index 00000000..965f8663 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -0,0 +1,825 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gv11b_h_ +#define _hw_pwr_gv11b_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a800 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a820 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h new file mode 100644 index 00000000..bcbb7b81 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -0,0 +1,765 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gv11b_h_ +#define _hw_ram_gv11b_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_vol_false_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_engine_wfi_mode_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_engine_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_wfi_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_engine_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_engine_wfi_target_local_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_engine_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_engine_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_engine_wfi_veid_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ram_in_engine_wfi_veid_w(void) +{ + return 134; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) +{ + return 136; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) +{ + return 137; +} +static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) +{ + return (v & 0x3) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) +{ + return (v & 0x1) << (2 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) +{ + return (v & 0x1) << (4 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) +{ + return (v & 0x1) << (5 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) +{ + return (v & 0x1) << (10 + i*0); +} +static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) +{ + return (v & 0x1) << (11 + i*0); +} +static inline u32 ram_in_sc_big_page_size__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_big_page_size_64kb_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) +{ + return (v & 0xfffff) << (12 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) +{ + return (v & 0xffffffff) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_sc_page_dir_base_target_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_big_page_size_0_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_sc_big_page_size_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) +{ + return 169; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_sem_addr_hi_w(void) +{ + return 14; +} +static inline u32 ram_fc_sem_addr_lo_w(void) +{ + return 15; +} +static inline u32 ram_fc_sem_payload_lo_w(void) +{ + return 16; +} +static inline u32 ram_fc_sem_payload_hi_w(void) +{ + return 39; +} +static inline u32 ram_fc_sem_execute_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_allowed_syncpoints_w(void) +{ + return 58; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_config_w(void) +{ + return 61; +} +static inline u32 ram_fc_runlist_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_fc_set_channel_info_w(void) +{ + return 63; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_channel_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_type_tsg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) +{ + return (v & 0x3) << 4; +} +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) +{ + return (v & 0x3) << 6; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_rl_entry_tsg_length_init_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_min_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_tsg_length_max_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h new file mode 100644 index 00000000..a3cfcf91 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gv11b_h_ +#define _hw_therm_gv11b_h_ + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h new file mode 100644 index 00000000..7d5750c2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gv11b_h_ +#define _hw_timer_gv11b_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h new file mode 100644 index 00000000..2e2ff6ba --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gv11b_h_ +#define _hw_top_gv11b_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy2_v(void) +{ + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 top_device_info_runlist_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 top_device_info_reset_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_entry_data_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_data_type_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 top_device_info_data_type_enum2_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_data_inst_id_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_data_pri_base_v(u32 r) +{ + return (r >> 12) & 0xfff; +} +static inline u32 top_device_info_data_pri_base_align_v(void) +{ + return 0x0000000c; +} +static inline u32 top_device_info_data_fault_id_enum_v(u32 r) +{ + return (r >> 3) & 0x7f; +} +static inline u32 top_device_info_data_fault_id_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_data_fault_id_valid_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h new file mode 100644 index 00000000..8bcf163f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_usermode_gv11b_h_ +#define _hw_usermode_gv11b_h_ + +static inline u32 usermode_cfg0_r(void) +{ + return 0x00810000; +} +static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 usermode_cfg0_usermode_class_id_value_v(void) +{ + return 0x0000c361; +} +static inline u32 usermode_time_0_r(void) +{ + return 0x00810080; +} +static inline u32 usermode_time_0_nsec_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 usermode_time_1_r(void) +{ + return 0x00810084; +} +static inline u32 usermode_time_1_nsec_f(u32 v) +{ + return (v & 0x1fffffff) << 0; +} +static inline u32 usermode_notify_channel_pending_r(void) +{ + return 0x00810090; +} +static inline u32 usermode_notify_channel_pending_id_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +#endif -- cgit v1.2.2 From d00b2000b5bb2f39e3610b8321e0872e2b06bd0a Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Jan 2017 16:18:47 -0800 Subject: gpu: nvgpu: gv11b: update zcull and pm pointers Update zcull and perfmon buffer pointers in context header. For gv11b maximum 49 bits gpu va possible. But, zcull and perfmon buffer pointers uses maximum 41 bit va address (258 bytes aligned). To accommodate this, high pointer registers needs to be updated in context header. JIRA GV11B-48 Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1291852 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 228bf5f2..a0f40de0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -186,6 +186,10 @@ static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) { return (v & 0x1ffff) << 0; } +static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) +{ + return 0x00000094; +} static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) { return 0x00000064; -- cgit v1.2.2 From f04a84b7ce976e911bf81497796016e149d17082 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 6 Feb 2017 15:57:12 -0800 Subject: gpu: nvgpu: gv11b: chip specific init_elcg_mode Added thermal registers for gv11b. Implemented chip specific init_elcg_mode. In thermal control register, engine power auto control config is removed and added new field for engine holdoff enable signal. JIRA GV11B-58 Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1300119 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 354 ++++++++++++++++++++- 1 file changed, 353 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index a3cfcf91..7be6d074 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -50,4 +50,356 @@ #ifndef _hw_therm_gv11b_h_ #define _hw_therm_gv11b_h_ +static inline u32 therm_use_a_r(void) +{ + return 0x00020798; +} +static inline u32 therm_use_a_ext_therm_0_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_use_a_ext_therm_1_enable_f(void) +{ + return 0x2; +} +static inline u32 therm_use_a_ext_therm_2_enable_f(void) +{ + return 0x4; +} +static inline u32 therm_evt_ext_therm_0_r(void) +{ + return 0x00020700; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_1_r(void) +{ + return 0x00020704; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_r(void) +{ + return 0x00020708; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_m(void) +{ + return 0x1 << 4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} #endif -- cgit v1.2.2 From 8497f45a2ed8599053ad0be99143c8effb510acf Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Feb 2017 15:58:01 -0800 Subject: nvgpu: gpu: gv11b: Remove syncpt protection support In gv11b sync point support is moved to a shim outside of GPU, and gv11b does not support sync points anymore. Remove use of the sync point protection. JIRA GV11B-47 JIRA GV11B-2 Change-Id: I70f3d2ce0cfe016453efe03f2bbf64c59baeb154 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1300964 Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 26 +--------------------- .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 4 ---- 2 files changed, 1 insertion(+), 29 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index c4d3a631..7aea3870 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -518,30 +518,6 @@ static inline u32 pbdma_udma_nop_r(void) { return 0x00000008; } -static inline u32 pbdma_allowed_syncpoints_r(u32 i) -{ - return 0x000400e8 + i*8192; -} -static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) -{ - return (v & 0x7fff) << 16; -} -static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) -{ - return (r >> 16) & 0x7fff; -} -static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) -{ - return (v & 0x7fff) << 0; -} static inline u32 pbdma_runlist_timeslice_r(u32 i) { return 0x000400f8 + i*8192; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index bcbb7b81..69de33c6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -546,10 +546,6 @@ static inline u32 ram_fc_subdevice_w(void) { return 37; } -static inline u32 ram_fc_allowed_syncpoints_w(void) -{ - return 58; -} static inline u32 ram_fc_target_w(void) { return 43; -- cgit v1.2.2 From 207e2ac7d12e62df476f4828136a4c15e156f8a6 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 22 Feb 2017 10:04:31 -0800 Subject: gpu: nvgpu: gv11b: reading max veid number To get maximum number of subctx, sw should read NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of LITTER_NUM_SUBCTX. JIRA GV11B-72 Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1309591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 12 ++++++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 6 +----- 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 656597ba..592a7899 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -462,6 +462,18 @@ static inline u32 gr_pri_fe_go_idle_info_r(void) { return 0x00404194; } +static inline u32 gr_pri_fe_chip_def_info_r(void) +{ + return 0x00404030; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) +{ + return 0x00000040; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { return 0x00504238; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 4e30447c..98acee4c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -114,10 +114,6 @@ static inline u32 proj_host_num_pbdma_v(void) { return 0x00000003; } -static inline u32 proj_litter_num_subctx_v(void) -{ - return 0x00000040; -} static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { return 0x00000004; -- cgit v1.2.2 From 2cc03def6a6427acdebd8a6053b1309280e5fe9b Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 28 Feb 2017 12:12:38 -0800 Subject: gpu: nvgpu: gv11b: update headers generate headers for pri ring, pbdma intr and gmmu with updated reg generator JIRA GV11B-47 JIRA GV11B-7 Change-Id: Id198fb338c03acc52c523754cfd07db01ff9bffd Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1312756 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 30 ++++++++- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 18 ++---- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 22 ++++++- .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 12 ++++ .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 18 +++++- .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 73 ++++++++++++++++++++++ .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 18 +++++- 7 files changed, 174 insertions(+), 17 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index d2f22afa..45cb0ad5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -826,6 +826,10 @@ static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) { return (v & 0xfffff) << 0; } +static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) +{ + return 0xfffff << 0; +} static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { return (r >> 0) & 0xfffff; @@ -1330,6 +1334,10 @@ static inline u32 fb_mmu_fault_status_replayable_set_f(void) { return 0x100; } +static inline u32 fb_mmu_fault_status_replayable_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) { return (v & 0x1) << 9; @@ -1346,6 +1354,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) { return 0x200; } +static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) { return (v & 0x1) << 10; @@ -1362,6 +1374,10 @@ static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) { return 0x400; } +static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) { return (v & 0x1) << 11; @@ -1378,6 +1394,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) { return 0x800; } +static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) { return (v & 0x1) << 12; @@ -1394,6 +1414,10 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) { return 0x1000; } +static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) { return (v & 0x1) << 13; @@ -1410,6 +1434,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) { return 0x2000; } +static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) { return (v & 0x1) << 14; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index d68c823a..911efa43 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -266,14 +266,6 @@ static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; } -static inline u32 fifo_gpc_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_hub_v(void) -{ - return 0x00000001; -} static inline u32 fifo_intr_pbdma_id_r(void) { return 0x000025a0; @@ -306,10 +298,6 @@ static inline u32 fifo_fb_timeout_period_max_f(void) { return 0x3fffffff; } -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262c; -} static inline u32 fifo_sched_disable_r(void) { return 0x00002630; @@ -406,6 +394,10 @@ static inline u32 fifo_engine_status_next_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_engine_status_eng_reload_v(u32 r) +{ + return (r >> 29) & 0x1; +} static inline u32 fifo_engine_status_faulted_v(u32 r) { return (r >> 30) & 0x1; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 1c523f87..dc8473a5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1274,6 +1274,26 @@ static inline u32 gmmu_pte_kind_s8_2s_v(void) { return 0x0000002b; } +static inline u32 gmmu_fault_client_type_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_client_type_hub_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_type_unbound_inst_block_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) +{ + return 0x0000001f; +} static inline u32 gmmu_fault_buf_size_v(void) { return 0x00000020; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 7aea3870..9c2ba7c6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -454,6 +454,10 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { return 0x80000; } +static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) +{ + return 0x100000; +} static inline u32 pbdma_intr_0_method_pending_f(void) { return 0x200000; @@ -466,6 +470,10 @@ static inline u32 pbdma_intr_0_device_pending_f(void) { return 0x800000; } +static inline u32 pbdma_intr_0_eng_reset_pending_f(void) +{ + return 0x1000000; +} static inline u32 pbdma_intr_0_semaphore_pending_f(void) { return 0x2000000; @@ -514,6 +522,10 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) { return 0x100; } +static inline u32 pbdma_intr_stall_1_r(u32 i) +{ + return 0x00040140 + i*8192; +} static inline u32 pbdma_udma_nop_r(void) { return 0x00000008; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index 835366c1..ce9e53ee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void) { return 0x00120058; } +static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) +{ + return (r >> 8) & 0x1; +} static inline u32 pri_ringmaster_intr_status1_r(void) { return 0x0012005c; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h new file mode 100644 index 00000000..89abfa3c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_gpc_gv11b_h_ +#define _hw_pri_ringstation_gpc_gv11b_h_ + +static inline u32 pri_ringstation_gpc_master_config_r(u32 i) +{ + return 0x00128300 + i*4; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) +{ + return 0x00128120; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) +{ + return 0x00128124; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) +{ + return 0x00128128; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) +{ + return 0x0012812c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index e192bd13..ae6ad795 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte { return 0x1; } +static inline u32 pri_ringstation_sys_priv_error_adr_r(void) +{ + return 0x00122120; +} +static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) +{ + return 0x00122124; +} +static inline u32 pri_ringstation_sys_priv_error_info_r(void) +{ + return 0x00122128; +} +static inline u32 pri_ringstation_sys_priv_error_code_r(void) +{ + return 0x0012212c; +} #endif -- cgit v1.2.2 From 434b1c588b9c8d61ac413b0c9ae402b483deb68b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 28 Feb 2017 16:17:04 -0800 Subject: gpu: nvgpu: gv11b: handle l2 related changes Implemented gv11b specific l2 state init and Configured ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info: - cbc_num_active_ltcs is read only for gv11b, so did not write any data to that field. - enforced serilized access to l2 from sysmem and peermem. - nvlink connected peer trafic sent through l2 JIRA GV11B-71 Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1312831 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 6968c699..45d3df07 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -174,6 +174,26 @@ static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { return 0x0017e27c; } +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) +{ + return (r >> 25) & 0x1; +} static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { return 0x0017e000; -- cgit v1.2.2 From 1bce980d09995947ff59b6d7f39cfaff51a70c74 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 21 Mar 2017 10:00:44 -0700 Subject: gpu: nvgpu: gv11b: init and implement reset_enable_hw -implement gv11b specific reset_enable_hw fifo ops -timeout period in fifo_fb_timeout_r() is set to init instead of max This register specifies the number of microseconds Host should wait for a response from FB before initiating a timeout interrupt. For bringup, this value should be set to a lower value than usual, such as ~.5 milliseconds (500), to help find out bugs in the memory subsystem. -timeout period in pbdma_timeout_r() is set to init instead of max This register contains a value used for detecting timeouts. The timeout value is in microsecond ticks. The timeouts that use this value are: GPfifo fetch timeouts to FB for acks, reqs, rdats. PBDMA connection to LB. GPfifo processor timeouts to FB for acks, reqs, rdats. Method processor timeouts to FB for acks, reqs, rdats. The init value is changed to 64K us based on bug 1816557. JIRA GPUT19X-74 JIRA GPUT19X-47 Change-Id: I6f818e129c3ea67571d206c5e735607cbfcf6ec6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1325352 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 4 ++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 911efa43..b9249128 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -298,6 +298,10 @@ static inline u32 fifo_fb_timeout_period_max_f(void) { return 0x3fffffff; } +static inline u32 fifo_fb_timeout_period_init_f(void) +{ + return 0x3c00; +} static inline u32 fifo_sched_disable_r(void) { return 0x00002630; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 9c2ba7c6..ed63cebc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -618,4 +618,20 @@ static inline u32 pbdma_set_channel_info_veid_f(u32 v) { return (v & 0x3f) << 8; } +static inline u32 pbdma_timeout_r(u32 i) +{ + return 0x0004012c + i*8192; +} +static inline u32 pbdma_timeout_period_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 pbdma_timeout_period_max_f(void) +{ + return 0xffffffff; +} +static inline u32 pbdma_timeout_period_init_f(void) +{ + return 0x10000; +} #endif -- cgit v1.2.2 From 2766420dfbe15e539a4b9514bbf41480fc636a28 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Mar 2017 15:04:29 -0700 Subject: gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo ops Context TSG teardown procedure: 1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE. This enables SW to determine whether a context has hung later in the process: otherwise, ongoing work on the runlist may keep ENG_STATUS from reaching a steady state. 2. Disable all channels in the TSG being torn down or submit a new runlist that does not contain the TSG. This is to prevent the TSG from being rescheduled once scheduling is reenabled in step 6. 3. Initiate a preempt of the engine by writing the bit associated with its runlist to NV_PFIFO_RUNLIST_PREEMPT. This allows to begin the preempt process prior to doing the slow register reads needed to determine whether the context has hit any interrupts or is hung. Do not poll NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete. 4. Check for interrupts or hangs while waiting for the preempt to complete. During the pbdma/eng preempt finish polling, any stalling interrupts relating to runlist must be detected and handled in order for the preemption to complete. 5. If a reset is needed as determined by step 4: a. Halt the memory interface for the engine (as per the relevant engine procedure). b. Reset the engine via NV_PMC_ENABLE. c. Take the engine out of reset and reinit the engine (as per relevant engine procedure) 6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE. JIRA GPUT19X-7 Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327931 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index b9249128..f05df49e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -318,6 +318,22 @@ static inline u32 fifo_sched_disable_true_v(void) { return 0x00000001; } +static inline u32 fifo_runlist_preempt_r(void) +{ + return 0x00002638; +} +static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_pending_v(void) +{ + return 0x00000001; +} static inline u32 fifo_preempt_r(void) { return 0x00002634; -- cgit v1.2.2 From 457f176785af5c8821889d00d89db05bbaf8f772 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 8 Mar 2017 22:34:49 -0800 Subject: gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout ops - detect and decode sched_error type. Any sched error starting with xxx_* is not supported in h/w and should never be seen by s/w - for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg is unknown. For other errors, just report error. - ctxsw timeout is not part of sched error fifo interrupt. A new fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling. Bug 1856152 JIRA GPUT19X-74 Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1317615 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index f05df49e..dbcb02c8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -230,6 +230,10 @@ static inline u32 fifo_intr_0_channel_intr_pending_f(void) { return 0x80000000; } +static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) +{ + return 0x2; +} static inline u32 fifo_intr_en_0_r(void) { return 0x00002140; @@ -242,6 +246,10 @@ static inline u32 fifo_intr_en_0_sched_error_m(void) { return 0x1 << 8; } +static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) +{ + return 0x2; +} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; @@ -266,6 +274,82 @@ static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; } +static inline u32 fifo_intr_ctxsw_timeout_r(void) +{ + return 0x00002a30; +} +static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) +{ + return 0x00000020; +} +static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) +{ + return 0x00003200 + i*4; +} +static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) +{ + return (r >> 4) & 0xfff; +} +static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) +{ + return 0x00000003; +} static inline u32 fifo_intr_pbdma_id_r(void) { return 0x000025a0; @@ -450,6 +534,26 @@ static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) { return 0x8000; } +static inline u32 fifo_eng_ctxsw_timeout_r(void) +{ + return 0x00002a0c; +} +static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) +{ + return 0x80000000; +} static inline u32 fifo_pbdma_status_r(u32 i) { return 0x00003080 + i*4; -- cgit v1.2.2 From 1d4b22ed88d2764b4708d27cbabcfbbdf9d04ba2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 17 Apr 2017 10:50:54 -0700 Subject: gpu: nvgpu: gv11b: set soc credits after fs_hub is out of reset Without these credits, gpu mmu binds over nvlink to soc are hanging. Also add l2_enabled for mc_elpg_enable. Bug 1899460 Change-Id: I0b26410d5c8ec9b4c88b319ddd9442f2fd91b321 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1463204 Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 20 ++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 6 +++++- 2 files changed, 25 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index dbcb02c8..bd2f628c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -630,4 +630,24 @@ static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) { return (r >> 16) & 0xff; } +static inline u32 fifo_fb_iface_r(void) +{ + return 0x000026f0; +} +static inline u32 fifo_fb_iface_control_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_fb_iface_control_enable_f(void) +{ + return 0x1; +} +static inline u32 fifo_fb_iface_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fifo_fb_iface_status_enabled_f(void) +{ + return 0x10; +} #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 98bec43a..f05910a9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -242,4 +242,8 @@ static inline u32 mc_elpg_enable_hub_enabled_f(void) { return 0x20000000; } +static inline u32 mc_elpg_enable_l2_enabled_f(void) +{ + return 0x8; +} #endif -- cgit v1.2.2 From d805731c8e333f16e42517cae50648954b99c870 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 20 Apr 2017 12:47:45 -0700 Subject: gpu: nvgpu: gv11b: hw header update for CL38424879 Bug 200300756 Change-Id: I2991d306905d2681cfb3031301e1b45a215ff89b Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1466955 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 20 -------------------- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 4 ---- 2 files changed, 24 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index dc8473a5..22ad23bc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -386,26 +386,6 @@ static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) { return 0x0000005f; } -static inline u32 gmmu_pte_kind_z16_4cz_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) -{ - return 0x0000000d; -} -static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) -{ - return 0x0000000e; -} -static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) -{ - return 0x0000000f; -} -static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) -{ - return 0x00000010; -} static inline u32 gmmu_pte_kind_s8z24_v(void) { return 0x00000011; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index f05910a9..38040723 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -142,10 +142,6 @@ static inline u32 mc_enable_pmedia_v(u32 r) { return (r >> 4) & 0x1; } -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20; -} static inline u32 mc_enable_ce0_m(void) { return 0x1 << 6; -- cgit v1.2.2 From 8c246cb18df28bac83297df2c9d0c47725b94273 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 5 May 2017 14:22:06 -0700 Subject: gpu: nvgpu: gv11b: MMU parity HWW error intr Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 45cb0ad5..76b4e902 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -462,6 +462,42 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { return 0x00000001; } +static inline u32 fb_mmu_l2tlb_ecc_status_r(void) +{ + return 0x00100e70; +} +static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_hubtlb_ecc_status_r(void) +{ + return 0x00100e84; +} +static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fillunit_ecc_status_r(void) +{ + return 0x00100e98; +} +static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) +{ + return 0x40000000; +} static inline u32 fb_niso_flush_sysmem_addr_r(void) { return 0x00100c10; @@ -526,6 +562,14 @@ static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_r(u32 i) { return 0x00100a24 + i*4; @@ -590,6 +634,14 @@ static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_set_r(u32 i) { return 0x00100a2c + i*4; @@ -654,6 +706,14 @@ static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_clr_r(u32 i) { return 0x00100a34 + i*4; @@ -718,6 +778,14 @@ static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) { return 0x00000000; -- cgit v1.2.2 From ffc37e50fa8e869e9a160b35f3cf414040e8a360 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 10 May 2017 12:38:08 +0530 Subject: gpu: nvgpu: gv11b: Add L1 tags parity support This CL covers the following parity support (corrected + uncorrected), 1) SM's L1 tags 2) SM's S2R's pixel PRF buffer 3) SM's L1 D-cache miss latency FIFOs Volta Resiliency Id - Volta-720, Volta-721, Volta-637 JIRA GPUT19X-85 JIRA GPUT19X-104 JIRA GPUT19X-100 JIRA GPUT19X-103 Bug 1825948 Bug 1825962 Bug 1775457 Change-Id: I53d7231a36b2c7c252395eca27b349eca80dec63 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1478881 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 592a7899..d45385a8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -482,6 +482,78 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { return 0x00504358; } +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) +{ + return 0x00504624; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) +{ + return 0x00504628; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) +{ + return 0x0050462c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { return 0x005042c4; -- cgit v1.2.2 From d503a234440b0b5912f64314de68689b3211bbcd Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Mon, 15 May 2017 15:32:21 +0530 Subject: gpu: nvgpu: gv11b: Add LRF + CBU parity support This CL covers the following parity support (uncorrected error), 1) SM's LRF 2) SM's CBU Volta Resiliency Id - Volta-637 JIRA GPUT19X-85 JIRA GPUT19X-110 Bug 1775457 Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1481791 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 172 +++++++++++++++++++++ 1 file changed, 172 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index d45385a8..4b2e8c32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -482,6 +482,106 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { return 0x00504358; } +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) +{ + return 0x1 << 13; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 26) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) +{ + return 0x0050435c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) +{ + return 0x00504360; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) { return 0x00504624; @@ -554,6 +654,78 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u { return (r >> 0) & 0xffff; } +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) +{ + return 0x00504638; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) +{ + return 0x0050463c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) +{ + return 0x00504640; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { return 0x005042c4; -- cgit v1.2.2 From 5a08eafbe076fba98de62883636ee6b0751cf7e9 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 17 May 2017 11:42:24 +0530 Subject: gpu: nvgpu: gv11b: Add L1 DATA + iCACHE parity This CL covers the following parity support (uncorrected error), 1) SM's L1 DATA 2) SM's L0 && L1 icache Volta Resiliency Id - Volta-634 JIRA GPUT19X-113 JIRA GPUT19X-99 Bug 1807553 Change-Id: Iacbf492028983529dadc5753007e43510b8cb786 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1483681 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 4b2e8c32..4ce69743 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -582,6 +582,134 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 { return (r >> 0) & 0xffff; } +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) +{ + return 0x0050436c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) +{ + return 0x00504370; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) +{ + return 0x00504374; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) +{ + return 0x0050464c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) +{ + return 0x00504650; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) +{ + return 0x00504654; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) { return 0x00504624; -- cgit v1.2.2 From 45ca7cb8c5774cfc15015973b1883faa1d93b9e6 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Fri, 19 May 2017 15:40:41 +0530 Subject: gpu: nvgpu: gv11b: Add GCC L1.5 parity support Add handling of GCC L1.5 parity exception. JIRA GPUT19X-86 Change-Id: Ie83fc306d3dff79b0ddaf2616dcf0ff71fccd4ca Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1485834 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 4ce69743..6f38cf5b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3370,6 +3370,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { return 0x0041ac94; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) +{ + return (v & 0x1) << 2; +} static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { return (v & 0xff) << 16; @@ -3378,6 +3382,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) +{ + return (r >> 2) & 0x1; +} static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { return (r >> 16) & 0xff; @@ -3386,6 +3394,62 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { return 0x00000001; } +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) +{ + return 0x00501048; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) +{ + return 0x0050104c; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) +{ + return 0x00501054; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; -- cgit v1.2.2 From 2173add7ae7210606afdaa56995a61d012b9a2f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 12 May 2017 11:07:00 -0700 Subject: gpu: nvgpu: per-chip GPCCS exception support Adding support for ISR handling of GPCCS exceptions and GCC ECC support JIRA: GPUT19X-83 Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1480997 Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 460 +++++++++++++++++++++ 1 file changed, 460 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 6f38cf5b..9917f86d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -1398,6 +1398,22 @@ static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { return (v & 0xffff) << 0; } +static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) +{ + return 0x1 << 21; +} +static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) +{ + return 0x1 << 22; +} static inline u32 gr_fecs_host_int_clear_r(void) { return 0x00409c20; @@ -3378,6 +3394,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { return (v & 0xff) << 16; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; @@ -3450,6 +3470,18 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { return (r >> 0) & 0xffff; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) +{ + return 0x4000; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; @@ -3954,4 +3986,432 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { return 0x1ff << 0; } +static inline u32 gr_gpc0_gpccs_hww_esr_r(void) +{ + return 0x00502c98; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) +{ + return 0x00502678; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) +{ + return 0x00502684; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) +{ + return (v & 0x7fffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) +{ + return 20; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) +{ + return 0xfffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) +{ + return 0x0050267c; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) +{ + return 0x00502680; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_status_r(void) +{ + return 0x00409678; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_falcon_ecc_address_r(void) +{ + return 0x00409684; +} +static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) +{ + return (v & 0x7fffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) +{ + return 20; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) +{ + return 0xfffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) +{ + return 0x0040967c; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) +{ + return 0x00409680; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} #endif -- cgit v1.2.2 From 77199c0225457c48acb2dca89d0bf93d05b33231 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 3 May 2017 13:55:27 -0700 Subject: gpu: nvgpu: gv11b: init enable_exceptions gr ops Enable FE, MEMFMT, DS and GPC exceptions only. Make sure corresponding HWW_ESR are enabled too. JIRA GPUT19X-75 Change-Id: Icf47b7e531dd72b59cbc6ac54b5902187f703d61 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1474859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 9917f86d..2d5afb29 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -194,6 +194,34 @@ static inline u32 gr_exception_en_fe_m(void) { return 0x1 << 0; } +static inline u32 gr_exception_en_fe_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_exception_en_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_en_gpc_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 gr_exception_en_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_en_memfmt_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_exception_en_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_en_ds_enabled_f(void) +{ + return 0x10; +} static inline u32 gr_exception1_en_r(void) { return 0x00400130; -- cgit v1.2.2 From 6bc36bded05ee497a474e5a718c49dc33eb235f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 22 May 2017 16:38:49 -0700 Subject: gpu: nvgpu: L2 cache tag ECC support Adding support for L2 cache tag ECC error handling JIRA: GPUT19X-112 Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1489029 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 184 +++++++++++++++++++++ 1 file changed, 184 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 45d3df07..1bcd1246 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -374,6 +374,190 @@ static inline u32 ltc_ltc0_lts0_intr_r(void) { return 0x0014040c; } +static inline u32 ltc_ltcs_ltss_intr3_r(void) +{ + return 0x0017e388; +} +static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) +{ + return 0x1 << 7; +} +static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) +{ + return 0x1 << 8; +} +static inline u32 ltc_ltc0_lts0_intr3_r(void) +{ + return 0x00140588; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) +{ + return 0x001404f0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) +{ + return 0x1 << 1; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) +{ + return 0x1 << 3; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) +{ + return 0x1 << 5; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) +{ + return 0x1 << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) +{ + return 0x1 << 2; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) +{ + return 0x1 << 4; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 19; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 17; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) +{ + return 0x001404fc; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) +{ + return 0x001404f4; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) +{ + return 0x001404f8; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) { return 0x0014051c; -- cgit v1.2.2 From 345eaef6a76771da9c3e8a5e375fc9d659fb1b2b Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 26 May 2017 08:31:46 -0700 Subject: gpu: nvgpu: GPC MMU ECC support Adding support for GPC MMU ECC error handling JIRA: GPUT19X-112 Change-Id: I62083bf2f144ff628ecd8c0aefc8d227a233ff36 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1490772 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 216 +++++++++++++++++++-- 1 file changed, 204 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 2d5afb29..62307265 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3426,6 +3426,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) { return (v & 0x1) << 14; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; @@ -3442,6 +3446,30 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) +{ + return 0x8000; +} static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) { return 0x00501048; @@ -3498,18 +3526,6 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { return (r >> 0) & 0xffff; } -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) -{ - return (v & 0x1) << 14; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) -{ - return 0x1 << 14; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) -{ - return 0x4000; -} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; @@ -4014,6 +4030,182 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { return 0x1ff << 0; } +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) +{ + return 0x00500324; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) +{ + return 0x00500314; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 17; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) +{ + return 0x00500320; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) +{ + return 0x00500318; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) +{ + return 0x0050031c; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} static inline u32 gr_gpc0_gpccs_hww_esr_r(void) { return 0x00502c98; -- cgit v1.2.2 From 3dc28cb1ab934ebcda33933086d7d0ffc8d1f907 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 26 May 2017 14:36:26 -0700 Subject: gpu: nvgpu: add chip specific ECC counters Add support for ECC counters for HUB MMU JIRA: GPUT19X-82 Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1490825 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 236 +++++++++++++++++++++ 1 file changed, 236 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 76b4e902..0ddccd45 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -466,6 +466,22 @@ static inline u32 fb_mmu_l2tlb_ecc_status_r(void) { return 0x00100e70; } +static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) { return (v & 0x1) << 30; @@ -474,10 +490,86 @@ static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) { return 0x40000000; } +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) +{ + return 0x00100e74; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) +{ + return 0x00100e78; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_l2tlb_ecc_address_r(void) +{ + return 0x00100e7c; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) +{ + return 32; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} static inline u32 fb_mmu_hubtlb_ecc_status_r(void) { return 0x00100e84; } +static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) { return (v & 0x1) << 30; @@ -486,10 +578,94 @@ static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) { return 0x40000000; } +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) +{ + return 0x00100e88; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) +{ + return 0x00100e8c; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_hubtlb_ecc_address_r(void) +{ + return 0x00100e90; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) +{ + return 32; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} static inline u32 fb_mmu_fillunit_ecc_status_r(void) { return 0x00100e98; } +static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) +{ + return 0x1 << 3; +} +static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) { return (v & 0x1) << 30; @@ -498,6 +674,66 @@ static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) { return 0x40000000; } +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) +{ + return 0x00100e9c; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) +{ + return 0x00100ea0; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_fillunit_ecc_address_r(void) +{ + return 0x00100ea4; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) +{ + return 32; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} static inline u32 fb_niso_flush_sysmem_addr_r(void) { return 0x00100c10; -- cgit v1.2.2 From 3bf38954c2cd794485ed1bac50df8e61ad1100eb Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 17 May 2017 20:03:22 -0700 Subject: gpu: nvgpu: gv11b: move cbc init to mmu from ltc Added cbc_init in fb and removed cbc_init from ltc. Also avoid writing into read only registers in ltc. GPUT19X-70 GPUT19X-116 Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1484525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 0ddccd45..e261ef14 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1814,4 +1814,84 @@ static inline u32 fb_mmu_fault_status_valid_clear_f(void) { return 0x80000000; } +static inline u32 fb_mmu_num_active_ltcs_r(void) +{ + return 0x00100ec0; +} +static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_cbc_base_r(void) +{ + return 0x00100ec4; +} +static inline u32 fb_mmu_cbc_base_address_f(u32 v) +{ + return (v & 0x3ffffff) << 0; +} +static inline u32 fb_mmu_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 fb_mmu_cbc_top_r(void) +{ + return 0x00100ec8; +} +static inline u32 fb_mmu_cbc_top_size_f(u32 v) +{ + return (v & 0x7fff) << 0; +} +static inline u32 fb_mmu_cbc_top_size_v(u32 r) +{ + return (r >> 0) & 0x7fff; +} +static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 fb_mmu_cbc_max_r(void) +{ + return 0x00100ecc; +} +static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 fb_mmu_cbc_max_safe_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_cbc_max_safe_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_cbc_max_safe_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) +{ + return 0x00000001; +} #endif -- cgit v1.2.2 From 366386d1898af61eb425aa8b37cfb656ff898c1a Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Jun 2017 14:47:20 +0530 Subject: gpu: nvgpu: add t19x specific nvhost abstraction files Add new abstraction file common/linux/nvhost_t19x.c for all nvhost APIs exported from linux/nvhost_t194.h This file will be compiled only if config CONFIG_TEGRA_GK20A_NVHOST is set Export the new headers from file Also add dummy private header file nvhost_priv_t19x.h to store definition of private structure nvgpu_nvhost_dev This file should be deleted when nvgpu-t19x repo is merged into common nvhost repo Jira NVGPU-29 Change-Id: I8c08c9242b08cc45f7c99cc400b3e1a720f9439c Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1493792 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h new file mode 100644 index 00000000..c456687b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_NVHOST_T19X_H__ +#define __NVGPU_NVHOST_T19X_H__ + +#ifdef CONFIG_TEGRA_GK20A_NVHOST +struct nvgpu_nvhost_dev; + +int nvgpu_nvhost_syncpt_unit_interface_get_aperture( + struct nvgpu_nvhost_dev *nvhost_dev, + phys_addr_t *base, + size_t *size); +u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); + +#endif +#endif /* __NVGPU_NVHOST_T19X_H__ */ -- cgit v1.2.2 From 12a8f51aa7a056d070861b120fc945d946bc10f9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 9 Jun 2017 16:19:17 -0700 Subject: gpu: nvgpu: gv11b: disable skedcheck18_l1_config_too_small SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL disabled Bug 200315442 Change-Id: I6d5c5f2fe6255d480350e01959c3c340579646e2 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1499568 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 62307265..29a8b33c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -4634,4 +4634,24 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { return (r >> 16) & 0xffff; } +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} #endif -- cgit v1.2.2 From af02a002457533bebf1f77d58b8f83867a1c0c1c Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 20 Apr 2017 14:56:25 +0530 Subject: gpu: nvgpu: gv11b hw header for Falcon controller Change-Id: I21fc23fe2b5636b295b7bd1a0ef96cfba713408f Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1466610 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 557 +++++++++++++++++++++ 1 file changed, 557 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h new file mode 100644 index 00000000..6bdc5fd1 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_falcon_gv11b_h_ +#define _hw_falcon_gv11b_h_ + +static inline u32 falcon_falcon_irqsset_r(void) +{ + return 0x00000000; +} +static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 falcon_falcon_irqsclr_r(void) +{ + return 0x00000004; +} +static inline u32 falcon_falcon_irqstat_r(void) +{ + return 0x00000008; +} +static inline u32 falcon_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 falcon_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 falcon_falcon_irqmode_r(void) +{ + return 0x0000000c; +} +static inline u32 falcon_falcon_irqmset_r(void) +{ + return 0x00000010; +} +static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 falcon_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 falcon_falcon_irqmclr_r(void) +{ + return 0x00000014; +} +static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_irqmask_r(void) +{ + return 0x00000018; +} +static inline u32 falcon_falcon_irqdest_r(void) +{ + return 0x0000001c; +} +static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 falcon_falcon_curctx_r(void) +{ + return 0x00000050; +} +static inline u32 falcon_falcon_nxtctx_r(void) +{ + return 0x00000054; +} +static inline u32 falcon_falcon_mailbox0_r(void) +{ + return 0x00000040; +} +static inline u32 falcon_falcon_mailbox1_r(void) +{ + return 0x00000044; +} +static inline u32 falcon_falcon_itfen_r(void) +{ + return 0x00000048; +} +static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 falcon_falcon_idlestate_r(void) +{ + return 0x0000004c; +} +static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 falcon_falcon_os_r(void) +{ + return 0x00000080; +} +static inline u32 falcon_falcon_engctl_r(void) +{ + return 0x000000a4; +} +static inline u32 falcon_falcon_cpuctl_r(void) +{ + return 0x00000100; +} +static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 falcon_falcon_cpuctl_alias_r(void) +{ + return 0x00000130; +} +static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_imemc_r(u32 i) +{ + return 0x00000180 + i*16; +} +static inline u32 falcon_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 falcon_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 falcon_falcon_imemd_r(u32 i) +{ + return 0x00000184 + i*16; +} +static inline u32 falcon_falcon_imemt_r(u32 i) +{ + return 0x00000188 + i*16; +} +static inline u32 falcon_falcon_sctl_r(void) +{ + return 0x00000240; +} +static inline u32 falcon_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 falcon_falcon_bootvec_r(void) +{ + return 0x00000104; +} +static inline u32 falcon_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 falcon_falcon_dmactl_r(void) +{ + return 0x0000010c; +} +static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_hwcfg_r(void) +{ + return 0x00000108; +} +static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 falcon_falcon_hwcfg1_r(void) +{ + return 0x0000012c; +} +static inline u32 falcon_falcon_hwcfg1_core_rev_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 falcon_falcon_hwcfg1_security_model_v(u32 r) +{ + return (r >> 4) & 0x3; +} +static inline u32 falcon_falcon_dmatrfbase_r(void) +{ + return 0x00000110; +} +static inline u32 falcon_falcon_dmatrfbase1_r(void) +{ + return 0x00000128; +} +static inline u32 falcon_falcon_dmatrfmoffs_r(void) +{ + return 0x00000114; +} +static inline u32 falcon_falcon_dmatrfcmd_r(void) +{ + return 0x00000118; +} +static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 falcon_falcon_dmatrffboffs_r(void) +{ + return 0x0000011c; +} +static inline u32 falcon_falcon_exterraddr_r(void) +{ + return 0x00000168; +} +static inline u32 falcon_falcon_exterrstat_r(void) +{ + return 0x0000016c; +} +static inline u32 falcon_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 falcon_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 falcon_falcon_icd_cmd_r(void) +{ + return 0x00000200; +} +static inline u32 falcon_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 falcon_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 falcon_falcon_icd_rdata_r(void) +{ + return 0x0000020c; +} +static inline u32 falcon_falcon_dmemc_r(u32 i) +{ + return 0x000001c0 + i*8; +} +static inline u32 falcon_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 falcon_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 falcon_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 falcon_falcon_dmemd_r(u32 i) +{ + return 0x000001c4 + i*8; +} +static inline u32 falcon_falcon_debug1_r(void) +{ + return 0x00000090; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) +{ + return 1; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) +{ + return 0x1 << 16; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) +{ + return 0x0; +} +static inline u32 falcon_falcon_debuginfo_r(void) +{ + return 0x00000094; +} +#endif -- cgit v1.2.2 From f500f45ebf7c658d67ec6001d2e88105d7e3f875 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 16:31:27 -0700 Subject: gpu: nvgpu: gv11b: implement ctxnotvalid pbdma_intr_1 Pbdma which encountered the ctxnotvalid interrupt will stall and prevent the channel which was loaded at the time the interrupt fired from being swapped out until the interrupt is cleared. CTXNOTVALID pbdma interrupt indicates error conditions related to the *_CTX_VALID fields for a channel. The following conditions trigger the interrupt: * CTX_VALID bit for the targeted engine is FALSE * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE JIRA GPUT19X-47 Change-Id: If65ce1fcdbaebd6b1d8313fdddf9e3e0fa51e885 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1329372 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index ed63cebc..abdbc17d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -502,6 +502,14 @@ static inline u32 pbdma_intr_1_r(u32 i) { return 0x00040148 + i*8192; } +static inline u32 pbdma_intr_1_ctxnotvalid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) +{ + return 0x80000000; +} static inline u32 pbdma_intr_en_0_r(u32 i) { return 0x0004010c + i*8192; -- cgit v1.2.2 From 5572bfa86a6afc7ae3c2f4a61e568f8e759c6ecc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 22 Jun 2017 14:43:05 -0700 Subject: gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG Added sw method for NVC397_SET_TEX_IN_DBG with following data fields: data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST Bug 1934197 Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1507479 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Tested-by: Wei Sun Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 29a8b33c..75a64be5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3830,6 +3830,38 @@ static inline u32 gr_zcull_subregion_qty_v(void) { return 0x00000010; } +static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) +{ + return 0x00419a00; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) +{ + return 0x00419bf0; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) +{ + return 0x1 << 10; +} static inline u32 gr_fe_pwr_mode_r(void) { return 0x00404170; -- cgit v1.2.2 From 56eaeab512fb848492d398e62ef55a2c963cc7a6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 3 May 2017 16:08:14 -0700 Subject: gpu: nvgpu: gv11b: sm stride litter added Required to support multiple SM JIRA GPUT19X-75 Change-Id: I1fd0530550ae14270a5e746d2efbf3e913ac4c3e Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1475985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: David Martinez Nieto --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 98acee4c..a6515ba9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -154,4 +154,8 @@ static inline u32 proj_scal_max_tpc_per_gpc_v(void) { return 0x00000008; } +static inline u32 proj_sm_stride_v(void) +{ + return 0x00000080; +} #endif -- cgit v1.2.2 From 11009e0e69a497780ddb918fab89da62089510ce Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 20 Jun 2017 15:31:46 -0700 Subject: gpu: nvgpu: gv11b: sm register changes gv11b has multiple SMs and SM register addresses have changed as compared to legacy chips. JIRA GPUT19X-75 Change-Id: I2319f4c78f3efda3430bab1f5ecf1a068e57a1ca Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1506013 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 318 +++++++++++---------- 1 file changed, 165 insertions(+), 153 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 75a64be5..daa4c08a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -174,6 +174,10 @@ static inline u32 gr_exception_ds_m(void) { return 0x1 << 4; } +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} static inline u32 gr_exception1_r(void) { return 0x00400118; @@ -966,14 +970,82 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) { return 0x80000000; } -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8; -} static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { return 0x00419eac; } +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x0050472c; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) +{ + return 0x00419eb4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) +{ + return 0x100; +} static inline u32 gr_fe_go_idle_timeout_r(void) { return 0x00404154; @@ -2422,6 +2494,22 @@ static inline u32 gr_sked_hww_esr_reset_active_f(void) { return 0x40000000; } +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} static inline u32 gr_cwd_fs_r(void) { return 0x00405b00; @@ -3302,90 +3390,74 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419f28; + return 0x00419ea8; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00504728; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { return 0x2; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { return 0x100; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { return 0x200; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { return 0x800; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { return 0x2000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { return 0x4000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { return 0x8000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { return 0x10000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { return 0x40000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { return 0x800000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { return 0x400000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x00419f2c; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40; -} static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { return 0x00419d0c; @@ -3562,10 +3634,22 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { return 0x00000000; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3574,6 +3658,10 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { return 0x8; @@ -3590,17 +3678,37 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) { return 0x00504708; } +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) +{ + return 0x0050470c; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) { return 0x00504710; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00504714; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) { return 0x00504718; } -static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) +{ + return 0x0050471c; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void) { - return 0x00419f10; + return 0x00419e90; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00419e94; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) +{ + return 0x00419e80; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { @@ -3618,46 +3726,6 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) -{ - return 0x00419f34; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { return 0x00504730; @@ -3686,6 +3754,18 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) +{ + return (r >> 1) & 0x1; +} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { return 0x00504738; @@ -3958,57 +4038,9 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { return 0x004188ac; } -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) +static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419f04; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1 << 3; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; + return 0x00419e84; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { @@ -4666,24 +4698,4 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { return (r >> 16) & 0xffff; } -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return 0x1 << 25; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1 << 8; -} #endif -- cgit v1.2.2 From f525ff15c4e8b5994201585ad584237b62bf3083 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 28 Jun 2017 10:05:04 -0700 Subject: gpu: nvgpu: gv11b: add ce interrupt handling Added handling for below ce interrupts -INVALID_CONFIG interrupt will be generated if a floorswept PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG registers. This is a fatal error and the LCE will have to be reset to get back to a working state. -MTHD_BUFFER_FAULT interrupt will be triggered if any access to a method buffer during context load or save encounters a fault. This is a fatal interrupt and will require at least the LCE to be reset before operations can start again, if not the entire GPU. JIRA GPUT19X-12 JIRA GPUT19X-46 Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1510298 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index 9f279207..fbf10b82 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -78,4 +78,24 @@ static inline u32 ce_intr_status_launcherr_reset_f(void) { return 0x4; } +static inline u32 ce_intr_status_invalid_config_pending_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_invalid_config_reset_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) +{ + return 0x10; +} +static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) +{ + return 0x10; +} +static inline u32 ce_pce_map_r(void) +{ + return 0x00104028; +} #endif -- cgit v1.2.2 From 690d560e65af8096bc391064631c74a3dd14fa89 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 30 Jun 2017 11:45:16 -0700 Subject: gpu: nvgpu: gv11b: Use sm dbgr bpt and warp mask 0/1 Instead of assuming mask_0 and mask_1 as consecutive registers, use mask_1 and mask_0 registers for reading/writing sm dbgr warp and bpt mask registers JIRA GPUT19X-75 Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1511736 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index daa4c08a..051961d2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3674,7 +3674,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) { return 0x00504708; } @@ -3682,7 +3682,7 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) { return 0x0050470c; } -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) { return 0x00504710; } @@ -3690,7 +3690,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) { return 0x00504714; } -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) { return 0x00504718; } @@ -3698,7 +3698,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) { return 0x0050471c; } -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) { return 0x00419e90; } -- cgit v1.2.2 From afa31cdd8cc6bb04faeed30b2cc30f5e6be888b5 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 3 Jul 2017 16:40:44 +0530 Subject: gpu: nvgpu: add support for L3 cache allocation of buffers Add gv11b implementation of gpu_phys_addr() that checks the t19x GMMU attributes struct to determine if L3 allocation should be enabled. If L3 alloc is enabled then a special physical address bit is set. Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct nvgpu_as_map_buffer_ex_args so that User space can add a hint to allocate buffer in L3 cache Jira GPUT19X-10 Bug 200279508 Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master/r/1512602 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h new file mode 100644 index 00000000..8e1a4846 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_GMMU_T19X_H__ +#define __NVGPU_GMMU_T19X_H__ + +struct nvgpu_gmmu_attrs; + +struct nvgpu_gmmu_attrs_t19x { + bool l3_alloc; +}; + +void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags); + +#endif -- cgit v1.2.2 From cf33b6c26bd054f5fe09be78ed754049821a8737 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 2 Jun 2017 09:06:42 -0700 Subject: gpu: nvgpu: gv11b: generated mmu fault fields/masks Generated h/w header for mmu fault handling JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I857ab6b67f6d9ac9a2c2ee982496dd0603bd010e Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1494842 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 268 ++++++++------------- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 8 + .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 10 +- 3 files changed, 113 insertions(+), 173 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index e261ef14..fd5427ec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -174,6 +174,10 @@ static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { return 0x10; } +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} static inline u32 fb_mmu_invalidate_sys_membar_s(void) { return 1; @@ -742,65 +746,65 @@ static inline u32 fb_niso_intr_r(void) { return 0x00100a20; } -static inline u32 fb_niso_intr_hub_access_counter_notify_f(u32 v) +static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return (v & 0x1) << 0; + return 0x1 << 0; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { return 0x1; } -static inline u32 fb_niso_intr_hub_access_counter_error_f(u32 v) +static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return (v & 0x1) << 1; + return 0x1 << 1; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { return 0x2; } -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return (v & 0x1) << 27; + return 0x1 << 27; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { return 0x8000000; } -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return (v & 0x1) << 28; + return 0x1 << 28; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { return 0x10000000; } -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return (v & 0x1) << 29; + return 0x1 << 29; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { return 0x20000000; } -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return (v & 0x1) << 30; + return 0x1 << 30; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { return 0x40000000; } -static inline u32 fb_niso_intr_mmu_other_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return (v & 0x1) << 31; + return 0x1 << 31; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { return 0x80000000; } -static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) { - return (v & 0x1) << 26; + return 0x1 << 26; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) { @@ -886,65 +890,65 @@ static inline u32 fb_niso_intr_en_set__size_1_v(void) { return 0x00000002; } -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return (v & 0x1) << 0; + return 0x1 << 0; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { return 0x1; } -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_f(u32 v) +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return (v & 0x1) << 1; + return 0x1 << 1; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { return 0x2; } -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return (v & 0x1) << 27; + return 0x1 << 27; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { return 0x8000000; } -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return (v & 0x1) << 28; + return 0x1 << 28; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { return 0x10000000; } -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return (v & 0x1) << 29; + return 0x1 << 29; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { return 0x20000000; } -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return (v & 0x1) << 30; + return 0x1 << 30; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { return 0x40000000; } -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return (v & 0x1) << 31; + return 0x1 << 31; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { return 0x80000000; } -static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) { - return (v & 0x1) << 26; + return 0x1 << 26; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) { @@ -958,65 +962,65 @@ static inline u32 fb_niso_intr_en_clr__size_1_v(void) { return 0x00000002; } -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return (v & 0x1) << 0; + return 0x1 << 0; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { return 0x1; } -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_f(u32 v) +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return (v & 0x1) << 1; + return 0x1 << 1; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { return 0x2; } -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return (v & 0x1) << 27; + return 0x1 << 27; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { return 0x8000000; } -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return (v & 0x1) << 28; + return 0x1 << 28; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { return 0x10000000; } -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return (v & 0x1) << 29; + return 0x1 << 29; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { return 0x20000000; } -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return (v & 0x1) << 30; + return 0x1 << 30; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { return 0x40000000; } -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return (v & 0x1) << 31; + return 0x1 << 31; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { return 0x80000000; } -static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) { - return (v & 0x1) << 26; + return 0x1 << 26; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) { @@ -1142,13 +1146,9 @@ static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) { return (v & 0x1) << 30; } -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_v(u32 r) +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_yes_v(void) -{ - return 0x00000001; + return 0x1 << 30; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { @@ -1162,17 +1162,9 @@ static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) { return (v & 0x1) << 31; } -static inline u32 fb_mmu_fault_buffer_get_overflow_v(u32 r) +static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_yes_f(void) -{ - return 0x80000000; + return 0x1 << 31; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { @@ -1290,6 +1282,10 @@ static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) { return (v & 0x1) << 31; } +static inline u32 fb_mmu_fault_buffer_size_enable_m(void) +{ + return 0x1 << 31; +} static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { return (r >> 31) & 0x1; @@ -1430,13 +1426,9 @@ static inline u32 fb_mmu_fault_status_r(void) { return 0x00100e60; } -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return (r >> 0) & 0x1; + return 0x1 << 0; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { @@ -1454,13 +1446,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) { return 0x1; } -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return (r >> 1) & 0x1; + return 0x1 << 1; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { @@ -1478,13 +1466,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) { return 0x2; } -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return (r >> 2) & 0x1; + return 0x1 << 2; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { @@ -1502,13 +1486,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) { return 0x4; } -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return (v & 0x1) << 3; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_v(u32 r) -{ - return (r >> 3) & 0x1; + return 0x1 << 3; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { @@ -1526,13 +1506,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) { return 0x8; } -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return (r >> 4) & 0x1; + return 0x1 << 4; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { @@ -1550,13 +1526,9 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) { return 0x10; } -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return (v & 0x1) << 5; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_v(u32 r) -{ - return (r >> 5) & 0x1; + return 0x1 << 5; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { @@ -1574,13 +1546,9 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) { return 0x20; } -static inline u32 fb_mmu_fault_status_dropped_other_phys_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return (v & 0x1) << 6; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_v(u32 r) -{ - return (r >> 6) & 0x1; + return 0x1 << 6; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { @@ -1598,13 +1566,9 @@ static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) { return 0x40; } -static inline u32 fb_mmu_fault_status_dropped_other_virt_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return (v & 0x1) << 7; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_v(u32 r) -{ - return (r >> 7) & 0x1; + return 0x1 << 7; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { @@ -1622,13 +1586,9 @@ static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) { return 0x80; } -static inline u32 fb_mmu_fault_status_replayable_f(u32 v) +static inline u32 fb_mmu_fault_status_replayable_m(void) { - return (v & 0x1) << 8; -} -static inline u32 fb_mmu_fault_status_replayable_v(u32 r) -{ - return (r >> 8) & 0x1; + return 0x1 << 8; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { @@ -1642,13 +1602,9 @@ static inline u32 fb_mmu_fault_status_replayable_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) -{ - return (v & 0x1) << 9; -} -static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) +static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return (r >> 9) & 0x1; + return 0x1 << 9; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { @@ -1662,13 +1618,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) +static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return (v & 0x1) << 10; -} -static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) -{ - return (r >> 10) & 0x1; + return 0x1 << 10; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { @@ -1682,13 +1634,9 @@ static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) +static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return (r >> 11) & 0x1; + return 0x1 << 11; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { @@ -1702,13 +1650,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) -{ - return (v & 0x1) << 12; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) +static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return (r >> 12) & 0x1; + return 0x1 << 12; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { @@ -1722,13 +1666,9 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) +static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return (v & 0x1) << 13; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) -{ - return (r >> 13) & 0x1; + return 0x1 << 13; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { @@ -1742,13 +1682,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return (v & 0x1) << 14; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) -{ - return (r >> 14) & 0x1; + return 0x1 << 14; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { @@ -1758,13 +1694,9 @@ static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) { return 0x4000; } -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return (r >> 15) & 0x1; + return 0x1 << 15; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { @@ -1774,13 +1706,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void { return 0x8000; } -static inline u32 fb_mmu_fault_status_busy_f(u32 v) +static inline u32 fb_mmu_fault_status_busy_m(void) { - return (v & 0x1) << 30; -} -static inline u32 fb_mmu_fault_status_busy_v(u32 r) -{ - return (r >> 30) & 0x1; + return 0x1 << 30; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { @@ -1790,13 +1718,9 @@ static inline u32 fb_mmu_fault_status_busy_true_f(void) { return 0x40000000; } -static inline u32 fb_mmu_fault_status_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_fault_status_valid_v(u32 r) +static inline u32 fb_mmu_fault_status_valid_m(void) { - return (r >> 31) & 0x1; + return 0x1 << 31; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 22ad23bc..383f7773 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1274,6 +1274,10 @@ static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) { return 0x0000001f; } +static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) +{ + return 0x0000000f; +} static inline u32 gmmu_fault_buf_size_v(void) { return 0x00000020; @@ -1458,6 +1462,10 @@ static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) { return 0x40000000; } +static inline u32 gmmu_fault_buf_entry_valid_m(void) +{ + return 0x1 << 31; +} static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) { return (r >> 31) & 0x1; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 2e2ff6ba..dbfc99b9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -94,6 +94,14 @@ static inline u32 top_num_ltcs_r(void) { return 0x00022454; } +static inline u32 top_num_ces_r(void) +{ + return 0x00022444; +} +static inline u32 top_num_ces_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} static inline u32 top_device_info_r(u32 i) { return 0x00022700 + i*4; -- cgit v1.2.2 From cc940da42f34568d6327ee20653725d11b1a3258 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 9 Jul 2017 14:00:24 -0700 Subject: gpu: nvgpu: gv11b: enable and handle mpc exception Implement gr ops to handle MPC exception triggered per TPC JIRA GPUT19X-69 Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1515915 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 051961d2..53dc7c87 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -902,6 +902,22 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { return 0x2; } +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) +{ + return 0x00504430; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) +{ + return 0x00504434; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) +{ + return (r >> 0) & 0x3f; +} static inline u32 gr_pri_be0_crop_status1_r(void) { return 0x00410134; @@ -3470,6 +3486,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) { return 0x1; } +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { return 0x0050450c; @@ -3482,6 +3502,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { return 0x2; } +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { return 0x0041ac94; @@ -3618,6 +3642,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) +{ + return 0x10; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { return 0x00504704; -- cgit v1.2.2 From 2272cedfbacf271a0faacfd054240fea3027423d Mon Sep 17 00:00:00 2001 From: Lauri Peltonen Date: Mon, 10 Jul 2017 15:06:31 +0300 Subject: gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw method The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5 Signed-off-by: Lauri Peltonen Reviewed-on: https://git-master.nvidia.com/r/1516205 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 53dc7c87..c9dbee52 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3918,6 +3918,30 @@ static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { return 0x1 << 31; } +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) +{ + return 0x4; +} static inline u32 gr_bes_crop_settings_r(void) { return 0x00408958; -- cgit v1.2.2 From 68b65f642ab49e8d30a17da04c053673e49e6d24 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sat, 8 Jul 2017 15:51:17 -0700 Subject: gpu: nvgpu: gv11b: h/w header updated for CL 38810810 H/w header updates for FPGA SNAP_0617 Change-Id: I6d3fe0b5b36de5999b09b9aa65e6dde2817634b5 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515766 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 12 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 122 ++++++++++++++++++++- 2 files changed, 125 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index bd2f628c..e98c9f76 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -266,10 +266,6 @@ static inline u32 fifo_intr_sched_error_code_f(u32 v) { return (v & 0xff) << 0; } -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000a; -} static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; @@ -308,7 +304,7 @@ static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 14) & 0x3; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) { @@ -324,15 +320,15 @@ static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) } static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) { - return (r >> 4) & 0xfff; + return (r >> 0) & 0x3fff; } static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16) & 0x3fff; } static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 30) & 0x3; } static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 965f8663..6c6dea4a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -78,6 +78,10 @@ static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) { return 0x40; } +static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) +{ + return 0x800; +} static inline u32 pwr_falcon_irqmode_r(void) { return 0x0010a00c; @@ -118,6 +122,38 @@ static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) { return (v & 0x1) << 7; } +static inline u32 pwr_falcon_irqmset_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 pwr_falcon_irqmclr_r(void) { return 0x0010a014; @@ -158,6 +194,34 @@ static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) { return (v & 0xff) << 8; } +static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 pwr_falcon_irqmask_r(void) { return 0x0010a018; @@ -202,6 +266,34 @@ static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) { return (v & 0xff) << 8; } +static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) { return (v & 0x1) << 16; @@ -238,6 +330,34 @@ static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) { return (v & 0xff) << 24; } +static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 31; +} static inline u32 pwr_falcon_curctx_r(void) { return 0x0010a050; -- cgit v1.2.2 From 4df5427c15e28a3bd131a4bdaed413de2a9a5e99 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 6 Jun 2017 22:56:11 -0700 Subject: gpu: nvgpu: gv11b: init perf related gr ops Implement gv11b specific perf gr ops JIRA GPUT19X-49 Bug 200311674 Change-Id: Ia65fe84df6e38e25f87d2c1b21c04b518c334d42 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1497402 GVS: Gerrit_Virtual_Submit Reviewed-by: Tushar Kashalikar Tested-by: Tushar Kashalikar Reviewed-by: Vijayakumar Subbu --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 152 +++++++++++++++++++++ 1 file changed, 152 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index c9dbee52..153aef2f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3998,6 +3998,158 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { return 0x1 << 10; } +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) +{ + return 0x00584200; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) +{ + return 0x00584204; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) +{ + return 0x00584208; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) +{ + return 0x00584210; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) +{ + return 0x00584214; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) +{ + return 0x00584218; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) +{ + return 0x0058421c; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) +{ + return 0x0058420c; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) +{ + return 0x00584220; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) +{ + return 0x00584224; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) +{ + return 0x00584228; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) +{ + return 0x0058422c; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) +{ + return 0x00584230; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) +{ + return 0x00584234; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) +{ + return 0x00584238; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) +{ + return 0x0058423c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) +{ + return 0x00584600; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) +{ + return 0x00584604; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) +{ + return 0x00584624; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) +{ + return 0x00584628; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) +{ + return 0x0058462c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) +{ + return 0x00584630; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) +{ + return 0x00584634; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) +{ + return 0x00584638; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) +{ + return 0x0058463c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) +{ + return 0x00584640; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) +{ + return 0x00584644; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) +{ + return 0x00584648; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) +{ + return 0x0058464c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) +{ + return 0x00584650; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) +{ + return 0x00584654; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) +{ + return 0x00584658; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) +{ + return 0x0058465c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) +{ + return 0x00584660; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) +{ + return 0x00584614; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) +{ + return 0x00584618; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) +{ + return 0x0058461c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) +{ + return 0x00584620; +} static inline u32 gr_fe_pwr_mode_r(void) { return 0x00404170; -- cgit v1.2.2 From de8e057f7eebcfe676278826ab457bf86b1b36fd Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: GV100 support Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 217 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 133 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 101 + .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 449 +++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 1469 ++++++++ .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 545 +++ .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 181 + .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 137 + .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 1281 +++++++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 3905 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 613 +++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 245 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 645 ++++ .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 205 + .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 57 + .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 161 + .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 73 + .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 85 + .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 161 + .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 929 +++++ .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 761 ++++ .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 293 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 109 + .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 229 ++ .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 89 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 137 + .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 201 + 27 files changed, 13411 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h new file mode 100644 index 00000000..c95d5af4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gv100_h_ +#define _hw_bus_gv100_h_ + +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h new file mode 100644 index 00000000..f64f542c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gv100_h_ +#define _hw_ccsr_gv100_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) +{ + return 0x400000; +} +static inline u32 ccsr_channel_eng_faulted_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 ccsr_channel_eng_faulted_reset_f(void) +{ + return 0x800000; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h new file mode 100644 index 00000000..26971f3f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gv100_h_ +#define _hw_ce_gv100_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_invalid_config_pending_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_invalid_config_reset_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) +{ + return 0x10; +} +static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) +{ + return 0x10; +} +static inline u32 ce_pce_map_r(void) +{ + return 0x00104028; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h new file mode 100644 index 00000000..f5593095 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gv100_h_ +#define _hw_ctxsw_prog_gv100_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) +{ + return 0x00000011; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) +{ + return 0x00000012; +} +static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) +{ + return 0x00000021; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7 << 0; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) +{ + return 0x00000060; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) +{ + return 0x00000094; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) +{ + return 0x00000064; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) +{ + return 0x00000070; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) +{ + return 0x00000074; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) +{ + return 0x00000078; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) +{ + return 0x0000007c; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) +{ + return 0x000000b8; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) +{ + return 0x000000bc; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) +{ + return 0x000000c0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) +{ + return 0x000000c4; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) +{ + return 0x000000c8; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) +{ + return 0x000000cc; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) +{ + return 0x000000e0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) +{ + return 0x000000e4; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h new file mode 100644 index 00000000..ce726633 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -0,0 +1,1469 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gv100_h_ +#define _hw_fb_gv100_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10; +} +static inline u32 fb_niso_intr_r(void) +{ + return 0x00100a20; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_r(u32 i) +{ + return 0x00100a24 + i*4; +} +static inline u32 fb_niso_intr_en__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_set_r(u32 i) +{ + return 0x00100a2c + i*4; +} +static inline u32 fb_niso_intr_en_set__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_r(u32 i) +{ + return 0x00100a34 + i*4; +} +static inline u32 fb_niso_intr_en_clr__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) +{ + return 0x00000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) +{ + return 0x00100e24 + i*20; +} +static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) +{ + return (r >> 1) & 0x3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x6; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) +{ + return 0x00100e28 + i*20; +} +static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_buffer_get_r(u32 i) +{ + return 0x00100e2c + i*20; +} +static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) +{ + return 0xfffff << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_put_r(u32 i) +{ + return 0x00100e30 + i*20; +} +static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_size_r(u32 i) +{ + return 0x00100e34 + i*20; +} +static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) +{ + return 0x20000000; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_addr_lo_r(void) +{ + return 0x00100e4c; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_addr_hi_r(void) +{ + return 0x00100e50; +} +static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_inst_lo_r(void) +{ + return 0x00100e54; +} +static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) +{ + return (r >> 10) & 0x3; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_inst_hi_r(void) +{ + return 0x00100e58; +} +static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_info_r(void) +{ + return 0x00100e5c; +} +static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fb_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 fb_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_info_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_r(void) +{ + return 0x00100e60; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) +{ + return 0x1 << 3; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) +{ + return 0x1 << 4; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) +{ + return 0x1 << 5; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) +{ + return 0x1 << 7; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_replayable_m(void) +{ + return 0x1 << 8; +} +static inline u32 fb_mmu_fault_status_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_set_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_fault_status_replayable_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_m(void) +{ + return 0x1 << 9; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) +{ + return 0x200; +} +static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_error_m(void) +{ + return 0x1 << 10; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) +{ + return 0x400; +} +static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) +{ + return 0x1 << 11; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) +{ + return 0x1 << 12; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) +{ + return 0x1000; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) +{ + return 0x1 << 13; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) +{ + return 0x2000; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) +{ + return 0x1 << 14; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) +{ + return 0x4000; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) +{ + return 0x1 << 15; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) +{ + return 0x8000; +} +static inline u32 fb_mmu_fault_status_busy_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_mmu_fault_status_busy_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_busy_true_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_status_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_status_valid_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_status_valid_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_local_memory_range_r(void) +{ + return 0x00100ce0; +} +static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) +{ + return (r >> 4) & 0x3f; +} +static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_niso_scrub_status_r(void) +{ + return 0x00100b20; +} +static inline u32 fb_niso_scrub_status_flag_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_priv_level_mask_r(void) +{ + return 0x00100cdc; +} +static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) +{ + return 0x1 << 7; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h new file mode 100644 index 00000000..9466a695 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gv100_h_ +#define _hw_fifo_gv100_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_userd_writeback_r(void) +{ + return 0x0000225c; +} +static inline u32 fifo_userd_writeback_timer_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_userd_writeback_timer_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_userd_writeback_timer_shorter_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_userd_writeback_timer_100us_v(void) +{ + return 0x00000064; +} +static inline u32 fifo_userd_writeback_timescale_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 fifo_userd_writeback_timescale_0_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_fb_timeout_period_init_f(void) +{ + return 0x3c00; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_runlist_preempt_r(void) +{ + return 0x00002638; +} +static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_pending_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x0000000f; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_eng_reload_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_cfg0_r(void) +{ + return 0x00002004; +} +static inline u32 fifo_cfg0_num_pbdma_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fifo_fb_iface_r(void) +{ + return 0x000026f0; +} +static inline u32 fifo_fb_iface_control_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_fb_iface_control_enable_f(void) +{ + return 0x1; +} +static inline u32 fifo_fb_iface_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fifo_fb_iface_status_enabled_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h new file mode 100644 index 00000000..c9b592bf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gv100_h_ +#define _hw_flush_gv100_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h new file mode 100644 index 00000000..b2b52ff2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gv100_h_ +#define _hw_fuse_gv100_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0xff << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h new file mode 100644 index 00000000..15bdde6c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -0,0 +1,1281 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gv100_h_ +#define _hw_gmmu_gv100_h_ + +static inline u32 gmmu_new_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_vol_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_vol_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_new_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_read_only_true_f(void) +{ + return 0x40; +} +static inline u32 gmmu_new_pte_comptagline_f(u32 v) +{ + return (v & 0x3ffff) << 4; +} +static inline u32 gmmu_new_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_kind_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gmmu_new_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +static inline u32 gmmu_fault_client_type_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_client_type_hub_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_type_unbound_inst_block_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) +{ + return 0x0000000f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h new file mode 100644 index 00000000..af1915b2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -0,0 +1,3905 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gv100_h_ +#define _hw_gr_gv100_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_en_fe_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_exception_en_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_en_gpc_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 gr_exception_en_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_en_memfmt_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_exception_en_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_en_ds_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x0050433c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419b3c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_fe_chip_def_info_r(void) +{ + return 0x00404030; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) +{ + return 0x00000040; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x00504358; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) +{ + return 0x1 << 13; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 26) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) +{ + return 0x0050435c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) +{ + return 0x00504360; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) +{ + return 0x0050436c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) +{ + return 0x00504370; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) +{ + return 0x00504374; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) +{ + return 0x00504638; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) +{ + return 0x0050463c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) +{ + return 0x00504640; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) +{ + return 0x00504430; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) +{ + return 0x00504434; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_address_veid_f(u32 v) +{ + return (v & 0x3f) << 20; +} +static inline u32 gr_pipe_bundle_address_veid_w(void) +{ + return 0; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) +{ + return 0x00419eac; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x0050472c; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) +{ + return 0x00419eb4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x1800; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fe_tpc_fs_r(u32 i) +{ + return 0x0040a200 + i*4; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} +static inline u32 gr_rstr2d_gpc_map_r(u32 i) +{ + return 0x0040780c + i*4; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x00001680; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00001680; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) +{ + return 0x00405830; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) +{ + return 0x0040585c; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000030; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000200; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0x3ff) << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0x3ff << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 10) & 0x3ff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504608; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x00504330; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00000d10; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419e04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000030; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x30; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x005001dc; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x000004b0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x005001d8; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x004181e4; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00418100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0041814c; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) +{ + return 0x0041815c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) +{ + return 0x00418198; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_gpc_map_r(u32 i) +{ + return 0x00418b08 + i*4; +} +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +{ + return (v & 0x1f) << 25; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +{ + return 0x00418980 + i*4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) +{ + return 0x00419ea8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00504728; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) +{ + return 0x00419d0c; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) +{ + return 0x0041ac94; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) +{ + return 0x00504704; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) +{ + return 0x00504708; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) +{ + return 0x0050470c; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) +{ + return 0x00504710; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00504714; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) +{ + return 0x00504718; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) +{ + return 0x0050471c; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) +{ + return 0x00419e90; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00419e94; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) +{ + return 0x00419e80; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) +{ + return 0x00504700; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) +{ + return 0x00504730; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) +{ + return 0xf << 24; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) +{ + return 0x00504738; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x005043a0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419ba0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x005043b0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419bb0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +{ + return 0x0041bf00 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) +{ + return 0x0041bfb0 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) +{ + return 0x00000005; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) +{ + return 0x4; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) +{ + return 0x00419a00; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) +{ + return 0x00419bf0; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) +{ + return 0x00419e84; +} +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419bd8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419ba4; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0x1ff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h new file mode 100644 index 00000000..f1d977d4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gv100_h_ +#define _hw_ltc_gv100_h_ + +static inline u32 ltc_pltcg_base_v(void) +{ + return 0x00140000; +} +static inline u32 ltc_pltcg_extent_v(void) +{ + return 0x0017ffff; +} +static inline u32 ltc_ltc0_ltss_v(void) +{ + return 0x00140200; +} +static inline u32 ltc_ltc0_lts0_v(void) +{ + return 0x00140400; +} +static inline u32 ltc_ltcs_ltss_v(void) +{ + return 0x0017e200; +} +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0003ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) +{ + return (r >> 25) & 0x1; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) +{ + return 0x0017e204; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) +{ + return 8; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_intr_r(void) +{ + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h new file mode 100644 index 00000000..0cd59c3b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gv100_h_ +#define _hw_mc_gv100_h_ + +static inline u32 mc_boot_0_r(void) +{ + return 0x00000000; +} +static inline u32 mc_boot_0_architecture_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 mc_boot_0_implementation_v(u32 r) +{ + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; +} +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_en_r(u32 i) +{ + return 0x00000140 + i*4; +} +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_elpg_enable_l2_enabled_f(void) +{ + return 0x8; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h new file mode 100644 index 00000000..ab363e94 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gv100_h_ +#define _hw_pbdma_gv100_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_config_r(u32 i) +{ + return 0x000400f4 + i*8192; +} +static inline u32 pbdma_config_l2_evict_first_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_l2_evict_normal_f(void) +{ + return 0x1; +} +static inline u32 pbdma_config_l2_evict_last_f(void) +{ + return 0x2; +} +static inline u32 pbdma_config_ce_split_enable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_ce_split_disable_f(void) +{ + return 0x10; +} +static inline u32 pbdma_config_auth_level_non_privileged_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_auth_level_privileged_f(void) +{ + return 0x100; +} +static inline u32 pbdma_config_userd_writeback_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_userd_writeback_enable_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_eng_reset_pending_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} +static inline u32 pbdma_intr_1_ctxnotvalid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_stall_1_r(u32 i) +{ + return 0x00040140 + i*8192; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_target_eng_ctx_valid_true_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_target_eng_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_ce_ctx_valid_true_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_target_ce_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) +{ + return 0x3000000; +} +static inline u32 pbdma_target_should_send_tsg_event_true_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_target_should_send_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_r(u32 i) +{ + return 0x000400fc + i*8192; +} +static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) +{ + return 0x1; +} +static inline u32 pbdma_set_channel_info_veid_f(u32 v) +{ + return (v & 0x3f) << 8; +} +static inline u32 pbdma_timeout_r(u32 i) +{ + return 0x0004012c + i*8192; +} +static inline u32 pbdma_timeout_period_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 pbdma_timeout_period_max_f(void) +{ + return 0xffffffff; +} +static inline u32 pbdma_timeout_period_init_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h new file mode 100644 index 00000000..f8e7c2a4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gv100_h_ +#define _hw_perf_gv100_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x0024a000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x0024a070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x0024a074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x0024a078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x0024a07c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x0024a084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x0024a088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x0024a0a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h new file mode 100644 index 00000000..88c70f53 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pram_gv100_h_ +#define _hw_pram_gv100_h_ + +static inline u32 pram_data032_r(u32 i) +{ + return 0x00700000 + i*4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h new file mode 100644 index 00000000..197fe550 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gv100_h_ +#define _hw_pri_ringmaster_gv100_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h new file mode 100644 index 00000000..eb77b4c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_gpc_gv100_h_ +#define _hw_pri_ringstation_gpc_gv100_h_ + +static inline u32 pri_ringstation_gpc_master_config_r(u32 i) +{ + return 0x00128300 + i*4; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) +{ + return 0x00128120; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) +{ + return 0x00128124; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) +{ + return 0x00128128; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) +{ + return 0x0012812c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h new file mode 100644 index 00000000..27feb5e9 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gv100_h_ +#define _hw_pri_ringstation_sys_gv100_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +static inline u32 pri_ringstation_sys_priv_error_adr_r(void) +{ + return 0x00122120; +} +static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) +{ + return 0x00122124; +} +static inline u32 pri_ringstation_sys_priv_error_info_r(void) +{ + return 0x00122128; +} +static inline u32 pri_ringstation_sys_priv_error_code_r(void) +{ + return 0x0012212c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h new file mode 100644 index 00000000..44e804e7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gv100_h_ +#define _hw_proj_gv100_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_fbpa_stride_v(void) +{ + return 0x00004000; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_engines_v(void) +{ + return 0x0000000f; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x0000000e; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000007; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000008; +} +static inline u32 proj_scal_litter_num_fbpas_v(void) +{ + return 0x00000010; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000006; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +static inline u32 proj_sm_stride_v(void) +{ + return 0x00000080; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h new file mode 100644 index 00000000..7d83b4ae --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -0,0 +1,929 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gv100_h_ +#define _hw_pwr_gv100_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) +{ + return 0x800; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmset_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a800 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a820 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h new file mode 100644 index 00000000..7fff981b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -0,0 +1,761 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gv100_h_ +#define _hw_ram_gv100_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_vol_false_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_engine_wfi_mode_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_engine_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_wfi_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_engine_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_engine_wfi_target_local_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_engine_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_engine_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_engine_wfi_veid_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ram_in_engine_wfi_veid_w(void) +{ + return 134; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) +{ + return 136; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) +{ + return 137; +} +static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) +{ + return (v & 0x3) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) +{ + return (v & 0x1) << (2 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) +{ + return (v & 0x1) << (4 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) +{ + return (v & 0x1) << (5 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) +{ + return (v & 0x1) << (10 + i*0); +} +static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) +{ + return (v & 0x1) << (11 + i*0); +} +static inline u32 ram_in_sc_big_page_size__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_big_page_size_64kb_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) +{ + return (v & 0xfffff) << (12 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) +{ + return (v & 0xffffffff) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_sc_page_dir_base_target_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_big_page_size_0_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_sc_big_page_size_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) +{ + return 169; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_sem_addr_hi_w(void) +{ + return 14; +} +static inline u32 ram_fc_sem_addr_lo_w(void) +{ + return 15; +} +static inline u32 ram_fc_sem_payload_lo_w(void) +{ + return 16; +} +static inline u32 ram_fc_sem_payload_hi_w(void) +{ + return 39; +} +static inline u32 ram_fc_sem_execute_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_config_w(void) +{ + return 61; +} +static inline u32 ram_fc_runlist_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_fc_set_channel_info_w(void) +{ + return 63; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_channel_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_type_tsg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) +{ + return (v & 0x3) << 4; +} +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) +{ + return (v & 0x3) << 6; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_rl_entry_tsg_length_init_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_min_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_tsg_length_max_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h new file mode 100644 index 00000000..d98002c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gv100_h_ +#define _hw_therm_gv100_h_ + +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_m(void) +{ + return 0x1 << 4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h new file mode 100644 index 00000000..c71e9a7d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gv100_h_ +#define _hw_timer_gv100_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h new file mode 100644 index 00000000..d993bddc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gv100_h_ +#define _hw_top_gv100_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_num_ces_r(void) +{ + return 0x00022444; +} +static inline u32 top_num_ces_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy2_v(void) +{ + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 top_device_info_runlist_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 top_device_info_reset_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_entry_data_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_data_type_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 top_device_info_data_type_enum2_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_data_inst_id_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_data_pri_base_v(u32 r) +{ + return (r >> 12) & 0xfff; +} +static inline u32 top_device_info_data_pri_base_align_v(void) +{ + return 0x0000000c; +} +static inline u32 top_device_info_data_fault_id_enum_v(u32 r) +{ + return (r >> 3) & 0x7f; +} +static inline u32 top_device_info_data_fault_id_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_data_fault_id_valid_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h new file mode 100644 index 00000000..86045e51 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_usermode_gv100_h_ +#define _hw_usermode_gv100_h_ + +static inline u32 usermode_cfg0_r(void) +{ + return 0x00810000; +} +static inline u32 usermode_cfg0_class_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 usermode_cfg0_class_id_value_v(void) +{ + return 0x0000c361; +} +static inline u32 usermode_time_0_r(void) +{ + return 0x00810080; +} +static inline u32 usermode_time_0_nsec_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 usermode_time_1_r(void) +{ + return 0x00810084; +} +static inline u32 usermode_time_1_nsec_f(u32 v) +{ + return (v & 0x1fffffff) << 0; +} +static inline u32 usermode_notify_channel_pending_r(void) +{ + return 0x00810090; +} +static inline u32 usermode_notify_channel_pending_id_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h new file mode 100644 index 00000000..4f15b39d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_xp_gv100_h_ +#define _hw_xp_gv100_h_ + +static inline u32 xp_dl_mgr_r(u32 i) +{ + return 0x0008b8c0 + i*4; +} +static inline u32 xp_dl_mgr_safe_timing_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 xp_pl_link_config_r(u32 i) +{ + return 0x0008c040 + i*4; +} +static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 xp_pl_link_config_ltssm_directive_m(void) +{ + return 0xf << 0; +} +static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) +{ + return 0x00000001; +} +static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) +{ + return (v & 0x3) << 18; +} +static inline u32 xp_pl_link_config_max_link_rate_m(void) +{ + return 0x3 << 18; +} +static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) +{ + return 0x00000002; +} +static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) +{ + return 0x00000001; +} +static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 xp_pl_link_config_target_tx_width_m(void) +{ + return 0x7 << 20; +} +static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) +{ + return 0x00000007; +} +static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) +{ + return 0x00000006; +} +static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) +{ + return 0x00000005; +} +static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) +{ + return 0x00000004; +} +static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) +{ + return 0x00000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h new file mode 100644 index 00000000..f082fdc7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_xve_gv100_h_ +#define _hw_xve_gv100_h_ + +static inline u32 xve_rom_ctrl_r(void) +{ + return 0x00000050; +} +static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) +{ + return 0x0; +} +static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) +{ + return 0x1; +} +static inline u32 xve_link_control_status_r(void) +{ + return 0x00000088; +} +static inline u32 xve_link_control_status_link_speed_m(void) +{ + return 0xf << 16; +} +static inline u32 xve_link_control_status_link_speed_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) +{ + return 0x00000001; +} +static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) +{ + return 0x00000002; +} +static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) +{ + return 0x00000003; +} +static inline u32 xve_link_control_status_link_width_m(void) +{ + return 0x3f << 20; +} +static inline u32 xve_link_control_status_link_width_v(u32 r) +{ + return (r >> 20) & 0x3f; +} +static inline u32 xve_link_control_status_link_width_x1_v(void) +{ + return 0x00000001; +} +static inline u32 xve_link_control_status_link_width_x2_v(void) +{ + return 0x00000002; +} +static inline u32 xve_link_control_status_link_width_x4_v(void) +{ + return 0x00000004; +} +static inline u32 xve_link_control_status_link_width_x8_v(void) +{ + return 0x00000008; +} +static inline u32 xve_link_control_status_link_width_x16_v(void) +{ + return 0x00000010; +} +static inline u32 xve_priv_xv_r(void) +{ + return 0x00000150; +} +static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 xve_priv_xv_cya_l0s_enable_m(void) +{ + return 0x1 << 7; +} +static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 xve_priv_xv_cya_l1_enable_m(void) +{ + return 0x1 << 8; +} +static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 xve_cya_2_r(void) +{ + return 0x00000704; +} +static inline u32 xve_reset_r(void) +{ + return 0x00000718; +} +static inline u32 xve_reset_reset_m(void) +{ + return 0x1 << 0; +} +static inline u32 xve_reset_gpu_on_sw_reset_m(void) +{ + return 0x1 << 1; +} +static inline u32 xve_reset_counter_en_m(void) +{ + return 0x1 << 2; +} +static inline u32 xve_reset_counter_val_f(u32 v) +{ + return (v & 0x7ff) << 4; +} +static inline u32 xve_reset_counter_val_m(void) +{ + return 0x7ff << 4; +} +static inline u32 xve_reset_counter_val_v(u32 r) +{ + return (r >> 4) & 0x7ff; +} +static inline u32 xve_reset_clock_on_sw_reset_m(void) +{ + return 0x1 << 15; +} +static inline u32 xve_reset_clock_counter_en_m(void) +{ + return 0x1 << 16; +} +static inline u32 xve_reset_clock_counter_val_f(u32 v) +{ + return (v & 0x7ff) << 17; +} +static inline u32 xve_reset_clock_counter_val_m(void) +{ + return 0x7ff << 17; +} +static inline u32 xve_reset_clock_counter_val_v(u32 r) +{ + return (r >> 17) & 0x7ff; +} +#endif -- cgit v1.2.2 From 78f1dac924221c9edbe51504b77e51caf2da7179 Mon Sep 17 00:00:00 2001 From: Sandarbh Jain Date: Wed, 9 Aug 2017 14:59:00 -0700 Subject: gpu: nvgpu: gv11b: PPC_IN_GPC_SHARED_BASE litter Adding missing GPU_LIT_PPC_IN_GPC_SHARED_BASE litter value Bug 1971835 Change-Id: If8851971ebea685fd6b3515b740aba8b64cae067 Signed-off-by: Sandarbh Jain Reviewed-on: https://git-master.nvidia.com/r/1536084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index a6515ba9..a17a7203 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -78,6 +78,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) { return 0x00003000; } +static inline u32 proj_ppc_in_gpc_shared_base_v(void) +{ + return 0x00003e00; +} static inline u32 proj_ppc_in_gpc_stride_v(void) { return 0x00000200; -- cgit v1.2.2 From c094ea161785a8c00bb2dc8c55e1a2bb8ffbcfc7 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 30 Aug 2017 15:03:25 +0530 Subject: gpu: nvgpu: gv11b: Secure boot support. This patch adds Secure boot support for T194. JIRA GPUT19X-5 Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1514558 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index 280a048a..b2801340 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -134,4 +134,12 @@ static inline u32 fuse_opt_feature_fuses_override_disable_r(void) { return 0x000213f0; } +static inline u32 fuse_opt_sec_debug_en_r(void) +{ + return 0x00021218; +} +static inline u32 fuse_opt_priv_sec_en_r(void) +{ + return 0x00021434; +} #endif -- cgit v1.2.2 From 52f50addc6cedf57fc3d8ff06314921499fb59e3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Sep 2017 17:35:03 +0530 Subject: gpu: nvgpu: add TSG enable/disable operations Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 36 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 38 +++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index f64f542c..664c0b80 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) { return (r >> 24) & 0xf; } +static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) +{ + return 0x00000002; +} +static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) +{ + return 0x00000004; +} +static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) +{ + return 0x0000000a; +} +static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) +{ + return 0x0000000b; +} +static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) +{ + return 0x0000000c; +} +static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) +{ + return 0x0000000d; +} +static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) +{ + return 0x0000000e; +} +static inline u32 ccsr_channel_next_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 ccsr_channel_next_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 618c4806..7e30c34b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) { return (r >> 24) & 0xf; } +static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) +{ + return 0x00000002; +} +static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) +{ + return 0x00000004; +} +static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) +{ + return 0x0000000a; +} +static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) +{ + return 0x0000000b; +} +static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) +{ + return 0x0000000c; +} +static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) +{ + return 0x0000000d; +} +static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) +{ + return 0x0000000e; +} +static inline u32 ccsr_channel_next_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 ccsr_channel_next_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; -- cgit v1.2.2 From f720b309f1ea87a301bcb216983396f3d9c55abc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Sep 2017 05:48:07 -0700 Subject: gpu: nvgpu: add tsg_verify_status_faulted operation Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 12 ++++++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 12 ++++++++++++ 2 files changed, 24 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index 664c0b80..dfebd60f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void) { return 0x00000001; } +static inline u32 ccsr_channel_force_ctx_reload_true_f(void) +{ + return 0x100; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; @@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v) { return (v & 0x1) << 23; } +static inline u32 ccsr_channel_eng_faulted_v(u32 r) +{ + return (r >> 23) & 0x1; +} static inline u32 ccsr_channel_eng_faulted_reset_f(void) { return 0x800000; } +static inline u32 ccsr_channel_eng_faulted_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_busy_v(u32 r) { return (r >> 28) & 0x1; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 7e30c34b..bd1e31c7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void) { return 0x00000001; } +static inline u32 ccsr_channel_force_ctx_reload_true_f(void) +{ + return 0x100; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; @@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v) { return (v & 0x1) << 23; } +static inline u32 ccsr_channel_eng_faulted_v(u32 r) +{ + return (r >> 23) & 0x1; +} static inline u32 ccsr_channel_eng_faulted_reset_f(void) { return 0x800000; } +static inline u32 ccsr_channel_eng_faulted_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_busy_v(u32 r) { return (r >> 28) & 0x1; -- cgit v1.2.2 From 31a50f07e4458b43f46a9612e4b27893a50d53b3 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 31 Aug 2017 11:15:50 -0700 Subject: gpu: nvgpu: gv11b: Set pbdma, fb and ctxsw timeout for pre-si fb and ctxsw timeout detection should be disabled for simulation architectures. Also set timeouts to max for pbdma, fb and ctxsw timeouts. Bug 200289427 Change-Id: I8723d5ee9ea2535f401b1972c8c14ffab8f9504a Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1549522 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index e98c9f76..04d6f0f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -382,6 +382,18 @@ static inline u32 fifo_fb_timeout_period_init_f(void) { return 0x3c00; } +static inline u32 fifo_fb_timeout_detection_m(void) +{ + return 0x1 << 31; +} +static inline u32 fifo_fb_timeout_detection_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_fb_timeout_detection_disabled_f(void) +{ + return 0x0; +} static inline u32 fifo_sched_disable_r(void) { return 0x00002630; @@ -538,18 +550,38 @@ static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) { return (v & 0x7fffffff) << 0; } +static inline u32 fifo_eng_ctxsw_timeout_period_m(void) +{ + return 0x7fffffff << 0; +} static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) { return (r >> 0) & 0x7fffffff; } +static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) +{ + return 0x3fffff; +} +static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) +{ + return 0x7fffffff; +} static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) { return (v & 0x1) << 31; } +static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) +{ + return 0x1 << 31; +} static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) { return 0x80000000; } +static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) +{ + return 0x0; +} static inline u32 fifo_pbdma_status_r(u32 i) { return 0x00003080 + i*4; -- cgit v1.2.2 From 39eb00dedac630f7945e22875d822a76d0caa578 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Sep 2017 11:31:08 +0530 Subject: gpu: nvgpu: gv11b faclon hw header update - Update CPUCTL register to add soft/hard reset support - Added debug registers JIRA NVGPU-56 Change-Id: Id867dd3a6085131917c2ada88f9899e415348038 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1564156 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 60 +++++++++++++++++----- 1 file changed, 48 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 6bdc5fd1..711c2b4b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -290,6 +290,14 @@ static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) { return (v & 0x1) << 1; } +static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) +{ + return (v & 0x1) << 3; +} static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) { return (v & 0x1) << 4; @@ -302,6 +310,10 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) { return (r >> 4) & 0x1; } +static inline u32 falcon_falcon_cpuctl_stopped_m(void) +{ + return 0x1 << 5; +} static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { return (v & 0x1) << 6; @@ -390,18 +402,6 @@ static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) { return (r >> 9) & 0x1ff; } -static inline u32 falcon_falcon_hwcfg1_r(void) -{ - return 0x0000012c; -} -static inline u32 falcon_falcon_hwcfg1_core_rev_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 falcon_falcon_hwcfg1_security_model_v(u32 r) -{ - return (r >> 4) & 0x3; -} static inline u32 falcon_falcon_dmatrfbase_r(void) { return 0x00000110; @@ -438,6 +438,42 @@ static inline u32 falcon_falcon_dmatrffboffs_r(void) { return 0x0000011c; } +static inline u32 falcon_falcon_imctl_debug_r(void) +{ + return 0x0000015c; +} +static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 falcon_falcon_imstat_r(void) +{ + return 0x00000144; +} +static inline u32 falcon_falcon_traceidx_r(void) +{ + return 0x00000148; +} +static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 falcon_falcon_traceidx_idx_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 falcon_falcon_tracepc_r(void) +{ + return 0x0000014c; +} +static inline u32 falcon_falcon_tracepc_pc_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} static inline u32 falcon_falcon_exterraddr_r(void) { return 0x00000168; -- cgit v1.2.2 From c359afbfe20cf7851ce93f70a95d652420d504cd Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 21 Sep 2017 12:56:41 -0700 Subject: gpu: nvgpu: Change HW header licenses to MIT JIRA NVGPU-218 Change-Id: I7e506649a5e32c54bf6880b575dedb63097ebb1b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1565708 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 24 ++++++++++------ .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 28 +++++++++++-------- .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 24 ++++++++++------ .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 24 ++++++++++------ .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 24 ++++++++++------ .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 26 +++++++++++------- .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 32 +++++++++++++--------- .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 24 ++++++++++------ .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 24 ++++++++++------ .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 24 ++++++++++------ .../include/nvgpu/hw/gv11b/hw_usermode_gv11b.h | 24 ++++++++++------ 53 files changed, 806 insertions(+), 488 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index c95d5af4..bc4f7f28 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index dfebd60f..ae0179f2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h index 26971f3f..6923d921 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h index f5593095..86075656 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index ce726633..33c08bad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h index 9466a695..1578a124 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h index c9b592bf..549c2f8f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h index b2b52ff2..0c2334da 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h index 15bdde6c..0aa2743d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index af1915b2..750070ad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h index f1d977d4..b5fc4b63 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 0cd59c3b..54bd1e35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index ab363e94..f0fc0773 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index f8e7c2a4..d9c8a348 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h index 88c70f53..3250bf3e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h index 197fe550..ca9da11d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h index eb77b4c0..70cf0461 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h index 27feb5e9..741e5bc2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index 44e804e7..ca851cd4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h index 7d83b4ae..b85c37aa 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index 7fff981b..fa42ebbe 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h index d98002c0..2834acf8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h index c71e9a7d..d53deb15 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index d993bddc..35b3ab33 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h index 86045e51..d49c9eed 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h index 4f15b39d..8680c11a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h index f082fdc7..534f66b3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h index 66571ae7..9fe7e591 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index bd1e31c7..3243e3e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index fbf10b82..8a0a9206 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index a0f40de0..27ac297c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 711c2b4b..fdeb4a37 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index fd5427ec..f902ae6c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 04d6f0f4..0d85a486 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h index 380f8824..b2938b32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index b2801340..6bc0604b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 383f7773..d84610f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 153aef2f..1af014f6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 1bcd1246..e1b0f47a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 38040723..7228cd8b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index abdbc17d..025a7af3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h index 836c014b..5adee5f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h index da2d4d2e..1568f310 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index ce9e53ee..24509b08 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index 89abfa3c..119e2075 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index ae6ad795..85b86c98 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index a17a7203..7e7ad14a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 6c6dea4a..43c0c908 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index 69de33c6..c7f15f57 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index 7be6d074..64a7e292 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h index 7d5750c2..1181f177 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index dbfc99b9..694257ed 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h index 8bcf163f..e3749690 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h | 24 +++++++++++++++--------- drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | 24 +++++++++++++++--------- 2 files changed, 30 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h index 8e1a4846..eea51fbb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __NVGPU_GMMU_T19X_H__ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h index c456687b..fcf99778 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __NVGPU_NVHOST_T19X_H__ -- cgit v1.2.2 From 9825a8ec69d54c725c38015006aed655d10ac567 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 15 Aug 2017 15:28:35 -0700 Subject: gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses Implemented litter values for following defines: GPU_LIT_SMPC_PRI_BASE GPU_LIT_SMPC_PRI_SHARED_BASE GPU_LIT_SMPC_PRI_UNIQUE_BASE9 GPU_LIT_SMPC_PRI_STRIDE Added broadcast flags for smpc Handled all combinations of broadcast/unicast EGPC, ETPC, SM Bug 200337994 Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1539075 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 7e7ad14a..8406ea21 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -116,6 +116,22 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) { return 0x00001800; } +static inline u32 proj_smpc_base_v(void) +{ + return 0x00000200; +} +static inline u32 proj_smpc_shared_base_v(void) +{ + return 0x00000300; +} +static inline u32 proj_smpc_unique_base_v(void) +{ + return 0x00000600; +} +static inline u32 proj_smpc_stride_v(void) +{ + return 0x00000100; +} static inline u32 proj_host_num_engines_v(void) { return 0x00000004; -- cgit v1.2.2 From 0d63e22a9920eb1e3d8653665cda650eca2311cd Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 27 Sep 2017 11:18:13 -0700 Subject: gpu: nvgpu: gv11b: check for memory aperture type Check for memory aperture type before setting relevant sysmem non-coherent or vidmem flags in ram entry. Modified following functions to correct memory aperture type: gv11b_get_ch_runlist_entry gv11b_subctx_commit_pdb Added following hw constants for chan_inst_target: ram_rl_entry_chan_inst_target_sys_mem_coh_v ram_rl_entry_chan_inst_target_vid_mem_v Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1569521 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 8 ++++++++ 2 files changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index fa42ebbe..3a5bf6cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -672,6 +672,14 @@ static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { return 0x00000003; } +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) +{ + return 0x00000002U; +} +static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) +{ + return 0x00000000U; +} static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { return (v & 0x3) << 6; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index c7f15f57..fe8bcd6b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -672,6 +672,14 @@ static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { return 0x00000003; } +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) +{ + return 0x00000002U; +} +static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) +{ + return 0x00000000U; +} static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { return (v & 0x3) << 6; -- cgit v1.2.2 From f63f96866dd3cd696e37cf7e83d419cca4f965fa Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 28 Sep 2017 16:57:16 -0700 Subject: gpu: nvgpu: gv11b: init therm regs for pwr/clk init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter* and *hubmmu_idle_filter* in therm regs. Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1570556 Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index 64a7e292..b47e37f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -240,6 +240,10 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { return 0x1f << 8; } +static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) +{ + return 0x200; +} static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { return (v & 0x7) << 13; @@ -248,6 +252,10 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { return 0x7 << 13; } +static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) +{ + return 0x2000; +} static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { return (v & 0xf) << 16; @@ -256,6 +264,10 @@ static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { return 0xf << 16; } +static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) +{ + return 0x40000; +} static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { return (v & 0xf) << 20; @@ -264,6 +276,10 @@ static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { return 0xf << 20; } +static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) +{ + return 0x0; +} static inline u32 therm_fecs_idle_filter_r(void) { return 0x00020288; @@ -272,6 +288,10 @@ static inline u32 therm_fecs_idle_filter_value_m(void) { return 0xffffffff << 0; } +static inline u32 therm_fecs_idle_filter_value__prod_f(void) +{ + return 0x0; +} static inline u32 therm_hubmmu_idle_filter_r(void) { return 0x0002028c; @@ -280,6 +300,10 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) { return 0xffffffff << 0; } +static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) +{ + return 0x0; +} static inline u32 therm_clk_slowdown_r(u32 i) { return 0x00020160 + i*4; -- cgit v1.2.2 From 3663e9cccc73589b1b2aa2148c8cb220bad99077 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 29 Sep 2017 20:09:55 +0530 Subject: gpu: nvgpu: gv100 hw header for Falcon controller - Constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions Change-Id: I039e269b18ea8aea48b30d3af84b347ae5509413 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1570998 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | 599 +++++++++++++++++++++ 1 file changed, 599 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h new file mode 100644 index 00000000..122956bb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h @@ -0,0 +1,599 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_falcon_gv100_h_ +#define _hw_falcon_gv100_h_ + +static inline u32 falcon_falcon_irqsset_r(void) +{ + return 0x00000000U; +} +static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40U; +} +static inline u32 falcon_falcon_irqsclr_r(void) +{ + return 0x00000004U; +} +static inline u32 falcon_falcon_irqstat_r(void) +{ + return 0x00000008U; +} +static inline u32 falcon_falcon_irqstat_halt_true_f(void) +{ + return 0x10U; +} +static inline u32 falcon_falcon_irqstat_exterr_true_f(void) +{ + return 0x20U; +} +static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40U; +} +static inline u32 falcon_falcon_irqmode_r(void) +{ + return 0x0000000cU; +} +static inline u32 falcon_falcon_irqmset_r(void) +{ + return 0x00000010U; +} +static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqmclr_r(void) +{ + return 0x00000014U; +} +static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_irqmask_r(void) +{ + return 0x00000018U; +} +static inline u32 falcon_falcon_irqdest_r(void) +{ + return 0x0000001cU; +} +static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1U) << 16U; +} +static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 17U; +} +static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1U) << 18U; +} +static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 19U; +} +static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1U) << 20U; +} +static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1U) << 21U; +} +static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1U) << 22U; +} +static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1U) << 23U; +} +static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xffU) << 24U; +} +static inline u32 falcon_falcon_curctx_r(void) +{ + return 0x00000050U; +} +static inline u32 falcon_falcon_nxtctx_r(void) +{ + return 0x00000054U; +} +static inline u32 falcon_falcon_mailbox0_r(void) +{ + return 0x00000040U; +} +static inline u32 falcon_falcon_mailbox1_r(void) +{ + return 0x00000044U; +} +static inline u32 falcon_falcon_itfen_r(void) +{ + return 0x00000048U; +} +static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1U; +} +static inline u32 falcon_falcon_idlestate_r(void) +{ + return 0x0000004cU; +} +static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1U) & 0x7fffU; +} +static inline u32 falcon_falcon_os_r(void) +{ + return 0x00000080U; +} +static inline u32 falcon_falcon_engctl_r(void) +{ + return 0x000000a4U; +} +static inline u32 falcon_falcon_cpuctl_r(void) +{ + return 0x00000100U; +} +static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1U << 4U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4U) & 0x1U; +} +static inline u32 falcon_falcon_cpuctl_stopped_m(void) +{ + return 0x1U << 5U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1U << 6U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6U) & 0x1U; +} +static inline u32 falcon_falcon_cpuctl_alias_r(void) +{ + return 0x00000130U; +} +static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_imemc_r(u32 i) +{ + return 0x00000180U + i*16U; +} +static inline u32 falcon_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3fU) << 2U; +} +static inline u32 falcon_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1U) << 24U; +} +static inline u32 falcon_falcon_imemd_r(u32 i) +{ + return 0x00000184U + i*16U; +} +static inline u32 falcon_falcon_imemt_r(u32 i) +{ + return 0x00000188U + i*16U; +} +static inline u32 falcon_falcon_sctl_r(void) +{ + return 0x00000240U; +} +static inline u32 falcon_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4U; +} +static inline u32 falcon_falcon_bootvec_r(void) +{ + return 0x00000104U; +} +static inline u32 falcon_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffffU) << 0U; +} +static inline u32 falcon_falcon_dmactl_r(void) +{ + return 0x0000010cU; +} +static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1U << 1U; +} +static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1U << 2U; +} +static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_hwcfg_r(void) +{ + return 0x00000108U; +} +static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0U) & 0x1ffU; +} +static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9U) & 0x1ffU; +} +static inline u32 falcon_falcon_dmatrfbase_r(void) +{ + return 0x00000110U; +} +static inline u32 falcon_falcon_dmatrfbase1_r(void) +{ + return 0x00000128U; +} +static inline u32 falcon_falcon_dmatrfmoffs_r(void) +{ + return 0x00000114U; +} +static inline u32 falcon_falcon_dmatrfcmd_r(void) +{ + return 0x00000118U; +} +static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7U) << 8U; +} +static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7U) << 12U; +} +static inline u32 falcon_falcon_dmatrffboffs_r(void) +{ + return 0x0000011cU; +} +static inline u32 falcon_falcon_imctl_debug_r(void) +{ + return 0x0000015cU; +} +static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) +{ + return (v & 0xffffffU) << 0U; +} +static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) +{ + return (v & 0x7U) << 24U; +} +static inline u32 falcon_falcon_imstat_r(void) +{ + return 0x00000144U; +} +static inline u32 falcon_falcon_traceidx_r(void) +{ + return 0x00000148U; +} +static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) +{ + return (r >> 16U) & 0xffU; +} +static inline u32 falcon_falcon_traceidx_idx_f(u32 v) +{ + return (v & 0xffU) << 0U; +} +static inline u32 falcon_falcon_tracepc_r(void) +{ + return 0x0000014cU; +} +static inline u32 falcon_falcon_tracepc_pc_v(u32 r) +{ + return (r >> 0U) & 0xffffffU; +} +static inline u32 falcon_falcon_exterraddr_r(void) +{ + return 0x00000168U; +} +static inline u32 falcon_falcon_exterrstat_r(void) +{ + return 0x0000016cU; +} +static inline u32 falcon_falcon_exterrstat_valid_m(void) +{ + return 0x1U << 31U; +} +static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} +static inline u32 falcon_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001U; +} +static inline u32 falcon_falcon_icd_cmd_r(void) +{ + return 0x00000200U; +} +static inline u32 falcon_falcon_icd_cmd_opc_s(void) +{ + return 4U; +} +static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xfU) << 0U; +} +static inline u32 falcon_falcon_icd_cmd_opc_m(void) +{ + return 0xfU << 0U; +} +static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0U) & 0xfU; +} +static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8U; +} +static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xeU; +} +static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1fU) << 8U; +} +static inline u32 falcon_falcon_icd_rdata_r(void) +{ + return 0x0000020cU; +} +static inline u32 falcon_falcon_dmemc_r(u32 i) +{ + return 0x000001c0U + i*8U; +} +static inline u32 falcon_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3fU) << 2U; +} +static inline u32 falcon_falcon_dmemc_offs_m(void) +{ + return 0x3fU << 2U; +} +static inline u32 falcon_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_dmemc_blk_m(void) +{ + return 0xffU << 8U; +} +static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1U) << 24U; +} +static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1U) << 25U; +} +static inline u32 falcon_falcon_dmemd_r(u32 i) +{ + return 0x000001c4U + i*8U; +} +static inline u32 falcon_falcon_debug1_r(void) +{ + return 0x00000090U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) +{ + return 1U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) +{ + return (v & 0x1U) << 16U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) +{ + return 0x1U << 16U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) +{ + return (r >> 16U) & 0x1U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) +{ + return 0x0U; +} +static inline u32 falcon_falcon_debuginfo_r(void) +{ + return 0x00000094U; +} +#endif -- cgit v1.2.2 From a61661172728fd0c173c1ebd73cc45233a1c23a4 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sat, 30 Sep 2017 12:51:51 +0530 Subject: gpu: nvgpu: falcon: Qualify unsigned HW constants - Falcon HW header re-generate for gv11b. - Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions Change-Id: I313945edac1112a32c965d9565b30dc95a002752 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1571352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 270 ++++++++++----------- 1 file changed, 135 insertions(+), 135 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index fdeb4a37..4bb8f2de 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -58,542 +58,542 @@ static inline u32 falcon_falcon_irqsset_r(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 falcon_falcon_irqsclr_r(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 falcon_falcon_irqstat_r(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 falcon_falcon_irqstat_halt_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 falcon_falcon_irqstat_exterr_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 falcon_falcon_irqmode_r(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 falcon_falcon_irqmset_r(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_irqmset_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 falcon_falcon_irqmclr_r(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_irqmask_r(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 falcon_falcon_irqdest_r(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 falcon_falcon_curctx_r(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 falcon_falcon_nxtctx_r(void) { - return 0x00000054; + return 0x00000054U; } static inline u32 falcon_falcon_mailbox0_r(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 falcon_falcon_mailbox1_r(void) { - return 0x00000044; + return 0x00000044U; } static inline u32 falcon_falcon_itfen_r(void) { - return 0x00000048; + return 0x00000048U; } static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 falcon_falcon_idlestate_r(void) { - return 0x0000004c; + return 0x0000004cU; } static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) { - return (r >> 1) & 0x7fff; + return (r >> 1U) & 0x7fffU; } static inline u32 falcon_falcon_os_r(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 falcon_falcon_engctl_r(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 falcon_falcon_cpuctl_r(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 falcon_falcon_cpuctl_stopped_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 falcon_falcon_cpuctl_alias_r(void) { - return 0x00000130; + return 0x00000130U; } static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_imemc_r(u32 i) { - return 0x00000180 + i*16; + return 0x00000180U + i*16U; } static inline u32 falcon_falcon_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 falcon_falcon_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 falcon_falcon_imemd_r(u32 i) { - return 0x00000184 + i*16; + return 0x00000184U + i*16U; } static inline u32 falcon_falcon_imemt_r(u32 i) { - return 0x00000188 + i*16; + return 0x00000188U + i*16U; } static inline u32 falcon_falcon_sctl_r(void) { - return 0x00000240; + return 0x00000240U; } static inline u32 falcon_falcon_mmu_phys_sec_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 falcon_falcon_bootvec_r(void) { - return 0x00000104; + return 0x00000104U; } static inline u32 falcon_falcon_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 falcon_falcon_dmactl_r(void) { - return 0x0000010c; + return 0x0000010cU; } static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_hwcfg_r(void) { - return 0x00000108; + return 0x00000108U; } static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) { - return (r >> 9) & 0x1ff; + return (r >> 9U) & 0x1ffU; } static inline u32 falcon_falcon_dmatrfbase_r(void) { - return 0x00000110; + return 0x00000110U; } static inline u32 falcon_falcon_dmatrfbase1_r(void) { - return 0x00000128; + return 0x00000128U; } static inline u32 falcon_falcon_dmatrfmoffs_r(void) { - return 0x00000114; + return 0x00000114U; } static inline u32 falcon_falcon_dmatrfcmd_r(void) { - return 0x00000118; + return 0x00000118U; } static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 falcon_falcon_dmatrffboffs_r(void) { - return 0x0000011c; + return 0x0000011cU; } static inline u32 falcon_falcon_imctl_debug_r(void) { - return 0x0000015c; + return 0x0000015cU; } static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 falcon_falcon_imstat_r(void) { - return 0x00000144; + return 0x00000144U; } static inline u32 falcon_falcon_traceidx_r(void) { - return 0x00000148; + return 0x00000148U; } static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 falcon_falcon_traceidx_idx_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 falcon_falcon_tracepc_r(void) { - return 0x0000014c; + return 0x0000014cU; } static inline u32 falcon_falcon_tracepc_pc_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 falcon_falcon_exterraddr_r(void) { - return 0x00000168; + return 0x00000168U; } static inline u32 falcon_falcon_exterrstat_r(void) { - return 0x0000016c; + return 0x0000016cU; } static inline u32 falcon_falcon_exterrstat_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 falcon_falcon_exterrstat_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 falcon_falcon_icd_cmd_r(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 falcon_falcon_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 falcon_falcon_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 falcon_falcon_icd_rdata_r(void) { - return 0x0000020c; + return 0x0000020cU; } static inline u32 falcon_falcon_dmemc_r(u32 i) { - return 0x000001c0 + i*8; + return 0x000001c0U + i*8U; } static inline u32 falcon_falcon_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 falcon_falcon_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 falcon_falcon_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_dmemc_blk_m(void) { - return 0xff << 8; + return 0xffU << 8U; } static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 falcon_falcon_dmemd_r(u32 i) { - return 0x000001c4 + i*8; + return 0x000001c4U + i*8U; } static inline u32 falcon_falcon_debug1_r(void) { - return 0x00000090; + return 0x00000090U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) { - return 1; + return 1U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 falcon_falcon_debuginfo_r(void) { - return 0x00000094; + return 0x00000094U; } #endif -- cgit v1.2.2 From f518304e0d8102216c7c0022cd4b66fcd844264c Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: fix GV100 hal definitions These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index bc4f7f28..2c89ccd6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -56,6 +56,10 @@ #ifndef _hw_bus_gv100_h_ #define _hw_bus_gv100_h_ +static inline u32 bus_sw_scratch_r(u32 i) +{ + return 0x00001580 + i*4; +} static inline u32 bus_bar0_window_r(void) { return 0x00001700; -- cgit v1.2.2 From 514c80d8d2d80cf9fa16447f7cd99d723ba5ce70 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 29 Sep 2017 12:39:57 -0700 Subject: gpu: nvgpu: gv11b: Qualify unsigned HW constants Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: Ic93ef7f7a6beae57be7759c7eb3df9148afed824 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1571162 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 82 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 64 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 24 +- .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 198 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 884 +++---- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 314 +-- .../nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 64 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 46 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 716 +++--- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 2428 ++++++++++---------- .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 372 +-- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 96 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 296 +-- .../nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 76 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 2 +- .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 54 +- .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 10 +- .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 16 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 64 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 446 ++-- .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 354 +-- .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 176 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 28 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 88 +- 24 files changed, 3449 insertions(+), 3449 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h index 9fe7e591..d1d9b34a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -58,166 +58,166 @@ static inline u32 bus_bar0_window_r(void) { - return 0x00001700; + return 0x00001700U; } static inline u32 bus_bar0_window_base_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 bus_bar0_window_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 bus_bar1_block_r(void) { - return 0x00001704; + return 0x00001704U; } static inline u32 bus_bar1_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar1_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar1_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar2_block_r(void) { - return 0x00001714; + return 0x00001714U; } static inline u32 bus_bar2_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar2_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar2_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar1_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bar2_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bind_status_r(void) { - return 0x00001710; + return 0x00001710U; } static inline u32 bus_bind_status_bar1_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 bus_bind_status_bar1_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_outstanding_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 bus_bind_status_bar2_pending_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 bus_bind_status_bar2_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_pending_busy_f(void) { - return 0x4; + return 0x4U; } static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 bus_bind_status_bar2_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_outstanding_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 bus_intr_0_r(void) { - return 0x00001100; + return 0x00001100U; } static inline u32 bus_intr_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 bus_intr_en_0_r(void) { - return 0x00001140; + return 0x00001140U; } static inline u32 bus_intr_en_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_en_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_en_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 3243e3e2..e21a4738 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -58,130 +58,130 @@ static inline u32 ccsr_channel_inst_r(u32 i) { - return 0x00800000 + i*8; + return 0x00800000U + i*8U; } static inline u32 ccsr_channel_inst__size_1_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ccsr_channel_inst_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 ccsr_channel_inst_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 ccsr_channel_inst_bind_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_bind_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 ccsr_channel_r(u32 i) { - return 0x00800004 + i*8; + return 0x00800004U + i*8U; } static inline u32 ccsr_channel__size_1_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ccsr_channel_enable_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ccsr_channel_enable_set_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ccsr_channel_enable_set_true_f(void) { - return 0x400; + return 0x400U; } static inline u32 ccsr_channel_enable_clr_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 ccsr_channel_status_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 ccsr_channel_next_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 ccsr_channel_next_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_force_ctx_reload_true_f(void) { - return 0x100; + return 0x100U; } static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 ccsr_channel_eng_faulted_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 ccsr_channel_eng_faulted_v(u32 r) { - return (r >> 23) & 0x1; + return (r >> 23U) & 0x1U; } static inline u32 ccsr_channel_eng_faulted_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 ccsr_channel_eng_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_busy_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index 8a0a9206..efc14d00 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -58,50 +58,50 @@ static inline u32 ce_intr_status_r(u32 i) { - return 0x00104410 + i*128; + return 0x00104410U + i*128U; } static inline u32 ce_intr_status_blockpipe_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_blockpipe_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_nonblockpipe_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_nonblockpipe_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_launcherr_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_launcherr_reset_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_invalid_config_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_invalid_config_reset_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_pce_map_r(void) { - return 0x00104028; + return 0x00104028U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 27ac297c..623a8c15 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -58,398 +58,398 @@ static inline u32 ctxsw_prog_fecs_header_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 ctxsw_prog_main_image_patch_count_o(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_context_id_o(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 ctxsw_prog_main_image_zcull_o(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_pm_o(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) { - return 0x8; + return 0x8U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) { - return 0x00000060; + return 0x00000060U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) { - return 0x00000094; + return 0x00000094U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) { - return 0x600dc0de; + return 0x600dc0deU; } static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_local_image_ppc_info_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_local_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) { - return 0xad0becab; + return 0xad0becabU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) { - return 2; + return 2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) { - return 0x2; + return 0x2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 ctxsw_prog_main_image_misc_options_o(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) { - return 0x2; + return 0x2U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index f902ae6c..ea3c7939 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -58,1770 +58,1770 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) { - return 0x00100800; + return 0x00100800U; } static inline u32 fb_mmu_ctrl_r(void) { - return 0x00100c80; + return 0x00100c80U; } static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) { - return (r >> 11) & 0x1; + return (r >> 11U) & 0x1U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_priv_mmu_phy_secure_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 fb_mmu_invalidate_pdb_r(void) { - return 0x00100cb8; + return 0x00100cb8U; } static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_invalidate_r(void) { - return 0x00100cbc; + return 0x00100cbcU; } static inline u32 fb_mmu_invalidate_all_va_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_invalidate_replay_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_replay_f(u32 v) { - return (v & 0x7) << 3; + return (v & 0x7U) << 3U; } static inline u32 fb_mmu_invalidate_replay_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 fb_mmu_invalidate_replay_v(u32 r) { - return (r >> 3) & 0x7; + return (r >> 3U) & 0x7U; } static inline u32 fb_mmu_invalidate_replay_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_replay_start_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_invalidate_sys_membar_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_invalidate_ack_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_invalidate_ack_f(u32 v) { - return (v & 0x3) << 7; + return (v & 0x3U) << 7U; } static inline u32 fb_mmu_invalidate_ack_m(void) { - return 0x3 << 7; + return 0x3U << 7U; } static inline u32 fb_mmu_invalidate_ack_v(u32 r) { - return (r >> 7) & 0x3; + return (r >> 7U) & 0x3U; } static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) { - return 6; + return 6U; } static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) { - return (v & 0x3f) << 9; + return (v & 0x3fU) << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) { - return 0x3f << 9; + return 0x3fU << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) { - return (r >> 9) & 0x3f; + return (r >> 9U) & 0x3fU; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) { - return 5; + return 5U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) { - return 0x1f << 15; + return 0x1fU << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) { - return 0x7 << 24; + return 0x7U << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) { - return (r >> 24) & 0x7; + return (r >> 24U) & 0x7U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) { - return 0x5000000; + return 0x5000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) { - return 0x6000000; + return 0x6000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) { - return 0x7000000; + return 0x7000000U; } static inline u32 fb_mmu_invalidate_trigger_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_trigger_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_invalidate_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_invalidate_trigger_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_invalidate_trigger_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_debug_wr_r(void) { - return 0x00100cc8; + return 0x00100cc8U; } static inline u32 fb_mmu_debug_wr_aperture_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_debug_wr_aperture_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_wr_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_wr_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_rd_r(void) { - return 0x00100ccc; + return 0x00100cccU; } static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_rd_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_ctrl_r(void) { - return 0x00100cc4; + return 0x00100cc4U; } static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 fb_mmu_debug_ctrl_debug_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_r(void) { - return 0x00100cd0; + return 0x00100cd0U; } static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_vpr_info_fetch_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_l2tlb_ecc_status_r(void) { - return 0x00100e70; + return 0x00100e70U; } static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) { - return 0x00100e74; + return 0x00100e74U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) { - return 0x00100e78; + return 0x00100e78U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_l2tlb_ecc_address_r(void) { - return 0x00100e7c; + return 0x00100e7cU; } static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) { - return 32; + return 32U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_hubtlb_ecc_status_r(void) { - return 0x00100e84; + return 0x00100e84U; } static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) { - return 0x00100e88; + return 0x00100e88U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) { - return 0x00100e8c; + return 0x00100e8cU; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_hubtlb_ecc_address_r(void) { - return 0x00100e90; + return 0x00100e90U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) { - return 32; + return 32U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fillunit_ecc_status_r(void) { - return 0x00100e98; + return 0x00100e98U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) { - return 0x00100e9c; + return 0x00100e9cU; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) { - return 0x00100ea0; + return 0x00100ea0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_fillunit_ecc_address_r(void) { - return 0x00100ea4; + return 0x00100ea4U; } static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) { - return 32; + return 32U; } static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_niso_flush_sysmem_addr_r(void) { - return 0x00100c10; + return 0x00100c10U; } static inline u32 fb_niso_intr_r(void) { - return 0x00100a20; + return 0x00100a20U; } static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1 << 26; + return 0x1U << 26U; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_r(u32 i) { - return 0x00100a24 + i*4; + return 0x00100a24U + i*4U; } static inline u32 fb_niso_intr_en__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) { - return (v & 0x1) << 26; + return (v & 0x1U) << 26U; } static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_set_r(u32 i) { - return 0x00100a2c + i*4; + return 0x00100a2cU + i*4U; } static inline u32 fb_niso_intr_en_set__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1 << 26; + return 0x1U << 26U; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_clr_r(u32 i) { - return 0x00100a34 + i*4; + return 0x00100a34U + i*4U; } static inline u32 fb_niso_intr_en_clr__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1 << 26; + return 0x1U << 26U; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) { - return 0x00100e24 + i*20; + return 0x00100e24U + i*20U; } static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 1; + return (v & 0x3U) << 1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) { - return (r >> 1) & 0x3; + return (r >> 1U) & 0x3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) { - return 0x00100e28 + i*20; + return 0x00100e28U + i*20U; } static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_buffer_get_r(u32 i) { - return 0x00100e2c + i*20; + return 0x00100e2cU + i*20U; } static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_put_r(u32 i) { - return 0x00100e30 + i*20; + return 0x00100e30U + i*20U; } static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_size_r(u32 i) { - return 0x00100e34 + i*20; + return 0x00100e34U + i*20U; } static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_addr_lo_r(void) { - return 0x00100e4c; + return 0x00100e4cU; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_addr_hi_r(void) { - return 0x00100e50; + return 0x00100e50U; } static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_inst_lo_r(void) { - return 0x00100e54; + return 0x00100e54U; } static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) { - return (r >> 10) & 0x3; + return (r >> 10U) & 0x3U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_inst_hi_r(void) { - return 0x00100e58; + return 0x00100e58U; } static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_info_r(void) { - return 0x00100e5c; + return 0x00100e5cU; } static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 fb_mmu_fault_info_client_v(u32 r) { - return (r >> 8) & 0x7f; + return (r >> 8U) & 0x7fU; } static inline u32 fb_mmu_fault_info_access_type_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 fb_mmu_fault_info_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_info_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_status_r(void) { - return 0x00100e60; + return 0x00100e60U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_replayable_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_set_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_fault_status_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) { - return 0x200; + return 0x200U; } static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) { - return 0x400; + return 0x400U; } static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fb_mmu_fault_status_busy_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_busy_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_status_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_status_valid_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_num_active_ltcs_r(void) { - return 0x00100ec0; + return 0x00100ec0U; } static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 fb_mmu_cbc_base_r(void) { - return 0x00100ec4; + return 0x00100ec4U; } static inline u32 fb_mmu_cbc_base_address_f(u32 v) { - return (v & 0x3ffffff) << 0; + return (v & 0x3ffffffU) << 0U; } static inline u32 fb_mmu_cbc_base_address_v(u32 r) { - return (r >> 0) & 0x3ffffff; + return (r >> 0U) & 0x3ffffffU; } static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 fb_mmu_cbc_top_r(void) { - return 0x00100ec8; + return 0x00100ec8U; } static inline u32 fb_mmu_cbc_top_size_f(u32 v) { - return (v & 0x7fff) << 0; + return (v & 0x7fffU) << 0U; } static inline u32 fb_mmu_cbc_top_size_v(u32 r) { - return (r >> 0) & 0x7fff; + return (r >> 0U) & 0x7fffU; } static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 fb_mmu_cbc_max_r(void) { - return 0x00100ecc; + return 0x00100eccU; } static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 fb_mmu_cbc_max_safe_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_cbc_max_safe_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_cbc_max_safe_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 0d85a486..59cc7a1d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -58,630 +58,630 @@ static inline u32 fifo_bar1_base_r(void) { - return 0x00002254; + return 0x00002254U; } static inline u32 fifo_bar1_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_bar1_base_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fifo_bar1_base_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_bar1_base_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_userd_writeback_r(void) { - return 0x0000225c; + return 0x0000225cU; } static inline u32 fifo_userd_writeback_timer_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_userd_writeback_timer_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_userd_writeback_timer_shorter_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_userd_writeback_timer_100us_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 fifo_userd_writeback_timescale_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 fifo_userd_writeback_timescale_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_runlist_base_r(void) { - return 0x00002270; + return 0x00002270U; } static inline u32 fifo_runlist_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_runlist_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 fifo_runlist_r(void) { - return 0x00002274; + return 0x00002274U; } static inline u32 fifo_runlist_engine_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 fifo_eng_runlist_base_r(u32 i) { - return 0x00002280 + i*8; + return 0x00002280U + i*8U; } static inline u32 fifo_eng_runlist_base__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_eng_runlist_r(u32 i) { - return 0x00002284 + i*8; + return 0x00002284U + i*8U; } static inline u32 fifo_eng_runlist__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_eng_runlist_length_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fifo_eng_runlist_length_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 fifo_eng_runlist_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_pb_timeslice_r(u32 i) { - return 0x00002350 + i*4; + return 0x00002350U + i*4U; } static inline u32 fifo_pb_timeslice_timeout_16_f(void) { - return 0x10; + return 0x10U; } static inline u32 fifo_pb_timeslice_timescale_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_pb_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_pbdma_map_r(u32 i) { - return 0x00002390 + i*4; + return 0x00002390U + i*4U; } static inline u32 fifo_intr_0_r(void) { - return 0x00002100; + return 0x00002100U; } static inline u32 fifo_intr_0_bind_error_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_bind_error_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_sched_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_sched_error_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_chsw_error_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_chsw_error_reset_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_lb_error_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_lb_error_reset_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_intr_0_runlist_event_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fifo_intr_0_channel_intr_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fifo_intr_en_0_r(void) { - return 0x00002140; + return 0x00002140U; } static inline u32 fifo_intr_en_0_sched_error_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 fifo_intr_en_0_sched_error_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fifo_intr_en_1_r(void) { - return 0x00002528; + return 0x00002528U; } static inline u32 fifo_intr_bind_error_r(void) { - return 0x0000252c; + return 0x0000252cU; } static inline u32 fifo_intr_sched_error_r(void) { - return 0x0000254c; + return 0x0000254cU; } static inline u32 fifo_intr_sched_error_code_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_intr_chsw_error_r(void) { - return 0x0000256c; + return 0x0000256cU; } static inline u32 fifo_intr_ctxsw_timeout_r(void) { - return 0x00002a30; + return 0x00002a30U; } static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) { - return 0x00003200 + i*4; + return 0x00003200U + i*4U; } static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) { - return (r >> 14) & 0x3; + return (r >> 14U) & 0x3U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) { - return (r >> 0) & 0x3fff; + return (r >> 0U) & 0x3fffU; } static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) { - return (r >> 16) & 0x3fff; + return (r >> 16U) & 0x3fffU; } static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) { - return (r >> 30) & 0x3; + return (r >> 30U) & 0x3U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_intr_pbdma_id_r(void) { - return 0x000025a0; + return 0x000025a0U; } static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_intr_runlist_r(void) { - return 0x00002a00; + return 0x00002a00U; } static inline u32 fifo_fb_timeout_r(void) { - return 0x00002a04; + return 0x00002a04U; } static inline u32 fifo_fb_timeout_period_m(void) { - return 0x3fffffff << 0; + return 0x3fffffffU << 0U; } static inline u32 fifo_fb_timeout_period_max_f(void) { - return 0x3fffffff; + return 0x3fffffffU; } static inline u32 fifo_fb_timeout_period_init_f(void) { - return 0x3c00; + return 0x3c00U; } static inline u32 fifo_fb_timeout_detection_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fifo_fb_timeout_detection_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_fb_timeout_detection_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_sched_disable_r(void) { - return 0x00002630; + return 0x00002630U; } static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_sched_disable_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_sched_disable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_runlist_preempt_r(void) { - return 0x00002638; + return 0x00002638U; } static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_preempt_r(void) { - return 0x00002634; + return 0x00002634U; } static inline u32 fifo_preempt_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_preempt_type_channel_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_preempt_type_tsg_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_preempt_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_preempt_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_engine_status_r(u32 i) { - return 0x00002640 + i*8; + return 0x00002640U + i*8U; } static inline u32 fifo_engine_status__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 fifo_engine_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_engine_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_engine_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_engine_status_ctx_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_engine_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_engine_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_engine_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_eng_reload_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fifo_engine_status_faulted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fifo_engine_status_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_engine_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fifo_engine_status_engine_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_engine_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fifo_eng_ctxsw_timeout_r(void) { - return 0x00002a0c; + return 0x00002a0cU; } static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) { - return (v & 0x7fffffff) << 0; + return (v & 0x7fffffffU) << 0U; } static inline u32 fifo_eng_ctxsw_timeout_period_m(void) { - return 0x7fffffff << 0; + return 0x7fffffffU << 0U; } static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) { - return (r >> 0) & 0x7fffffff; + return (r >> 0U) & 0x7fffffffU; } static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) { - return 0x3fffff; + return 0x3fffffU; } static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) { - return 0x7fffffff; + return 0x7fffffffU; } static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_pbdma_status_r(u32 i) { - return 0x00003080 + i*4; + return 0x00003080U + i*4U; } static inline u32 fifo_pbdma_status__size_1_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_pbdma_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_pbdma_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_pbdma_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_pbdma_status_chan_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_pbdma_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_chsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_cfg0_r(void) { - return 0x00002004; + return 0x00002004U; } static inline u32 fifo_cfg0_num_pbdma_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fifo_fb_iface_r(void) { - return 0x000026f0; + return 0x000026f0U; } static inline u32 fifo_fb_iface_control_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fifo_fb_iface_control_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_fb_iface_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 fifo_fb_iface_status_enabled_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h index b2938b32..45c01de0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -58,130 +58,130 @@ static inline u32 flush_l2_system_invalidate_r(void) { - return 0x00070004; + return 0x00070004U; } static inline u32 flush_l2_system_invalidate_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_system_invalidate_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_system_invalidate_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_r(void) { - return 0x00070010; + return 0x00070010U; } static inline u32 flush_l2_flush_dirty_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_flush_dirty_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_r(void) { - return 0x0007000c; + return 0x0007000cU; } static inline u32 flush_l2_clean_comptags_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_clean_comptags_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_r(void) { - return 0x00070000; + return 0x00070000U; } static inline u32 flush_fb_flush_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_fb_flush_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_fb_flush_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_fb_flush_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index 6bc0604b..f8d9b196 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -58,94 +58,94 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) { - return 0x00021c38 + i*4; + return 0x00021c38U + i*4U; } static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) { - return 0x00021838 + i*4; + return 0x00021838U + i*4U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) { - return 0x00021944; + return 0x00021944U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) { - return 0x00021948; + return 0x00021948U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) { - return 0x1; + return 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fuse_status_opt_fbio_r(void) { - return 0x00021c14; + return 0x00021c14U; } static inline u32 fuse_status_opt_fbio_data_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fuse_status_opt_fbio_data_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fuse_status_opt_fbio_data_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) { - return 0x00021d70 + i*4; + return 0x00021d70U + i*4U; } static inline u32 fuse_status_opt_fbp_r(void) { - return 0x00021d38; + return 0x00021d38U; } static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fuse_opt_ecc_en_r(void) { - return 0x00021228; + return 0x00021228U; } static inline u32 fuse_opt_feature_fuses_override_disable_r(void) { - return 0x000213f0; + return 0x000213f0U; } static inline u32 fuse_opt_sec_debug_en_r(void) { - return 0x00021218; + return 0x00021218U; } static inline u32 fuse_opt_priv_sec_en_r(void) { - return 0x00021434; + return 0x00021434U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index d84610f3..c39cc2d8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -58,1434 +58,1434 @@ static inline u32 gmmu_new_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_aperture_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pde_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pde_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_pde__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_vol_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_vol_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde__size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gmmu_new_pte__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_pte_valid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_valid_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gmmu_new_pte_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_privilege_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_privilege_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 gmmu_new_pte_privilege_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_address_vid_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_vid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pte_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pte_read_only_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_read_only_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 gmmu_new_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 4; + return (v & 0x3ffffU) << 4U; } static inline u32 gmmu_new_pte_comptagline_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_kind_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gmmu_new_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_pte_kind_f(u32 v) { - return (v & 0xff) << 4; + return (v & 0xffU) << 4U; } static inline u32 gmmu_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_pte_kind_invalid_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 gmmu_pte_kind_pitch_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_pte_kind_z16_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_pte_kind_z16_2c_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 gmmu_pte_kind_z16_2z_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 gmmu_pte_kind_z16_2cz_v(void) { - return 0x00000036; + return 0x00000036U; } static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) { - return 0x00000037; + return 0x00000037U; } static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) { - return 0x0000005f; + return 0x0000005fU; } static inline u32 gmmu_pte_kind_s8z24_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 gmmu_pte_kind_s8z24_1z_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) { - return 0x00000017; + return 0x00000017U; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) { - return 0x00000019; + return 0x00000019U; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) { - return 0x0000001b; + return 0x0000001bU; } static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) { - return 0x0000001d; + return 0x0000001dU; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) { - return 0x0000001e; + return 0x0000001eU; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) { - return 0x00000022; + return 0x00000022U; } static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) { - return 0x00000023; + return 0x00000023U; } static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) { - return 0x00000024; + return 0x00000024U; } static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) { - return 0x00000026; + return 0x00000026U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) { - return 0x00000027; + return 0x00000027U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) { - return 0x00000029; + return 0x00000029U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) { - return 0x0000002e; + return 0x0000002eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) { - return 0x0000002f; + return 0x0000002fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) { - return 0x00000033; + return 0x00000033U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) { - return 0x00000034; + return 0x00000034U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) { - return 0x00000035; + return 0x00000035U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) { - return 0x0000003b; + return 0x0000003bU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) { - return 0x0000003d; + return 0x0000003dU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) { - return 0x0000003e; + return 0x0000003eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) { - return 0x0000003f; + return 0x0000003fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) { - return 0x00000041; + return 0x00000041U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) { - return 0x00000042; + return 0x00000042U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) { - return 0x00000043; + return 0x00000043U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) { - return 0x00000044; + return 0x00000044U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) { - return 0x00000045; + return 0x00000045U; } static inline u32 gmmu_pte_kind_z24s8_v(void) { - return 0x00000046; + return 0x00000046U; } static inline u32 gmmu_pte_kind_z24s8_1z_v(void) { - return 0x00000047; + return 0x00000047U; } static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) { - return 0x00000048; + return 0x00000048U; } static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) { - return 0x00000049; + return 0x00000049U; } static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) { - return 0x0000004a; + return 0x0000004aU; } static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) { - return 0x0000004b; + return 0x0000004bU; } static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) { - return 0x0000004c; + return 0x0000004cU; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) { - return 0x0000004d; + return 0x0000004dU; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) { - return 0x0000004e; + return 0x0000004eU; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) { - return 0x0000004f; + return 0x0000004fU; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) { - return 0x00000051; + return 0x00000051U; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) { - return 0x00000052; + return 0x00000052U; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) { - return 0x00000053; + return 0x00000053U; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) { - return 0x00000054; + return 0x00000054U; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) { - return 0x00000055; + return 0x00000055U; } static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) { - return 0x00000056; + return 0x00000056U; } static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) { - return 0x00000057; + return 0x00000057U; } static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) { - return 0x00000058; + return 0x00000058U; } static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) { - return 0x00000059; + return 0x00000059U; } static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) { - return 0x0000005a; + return 0x0000005aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) { - return 0x0000005b; + return 0x0000005bU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) { - return 0x0000005c; + return 0x0000005cU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) { - return 0x0000005d; + return 0x0000005dU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) { - return 0x0000005e; + return 0x0000005eU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) { - return 0x00000063; + return 0x00000063U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) { - return 0x00000065; + return 0x00000065U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) { - return 0x00000066; + return 0x00000066U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) { - return 0x00000067; + return 0x00000067U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) { - return 0x00000069; + return 0x00000069U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) { - return 0x0000006a; + return 0x0000006aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) { - return 0x0000006f; + return 0x0000006fU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) { - return 0x00000071; + return 0x00000071U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) { - return 0x00000072; + return 0x00000072U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) { - return 0x00000073; + return 0x00000073U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) { - return 0x00000075; + return 0x00000075U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) { - return 0x00000076; + return 0x00000076U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) { - return 0x00000077; + return 0x00000077U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) { - return 0x00000079; + return 0x00000079U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) { - return 0x0000007a; + return 0x0000007aU; } static inline u32 gmmu_pte_kind_zf32_v(void) { - return 0x0000007b; + return 0x0000007bU; } static inline u32 gmmu_pte_kind_zf32_1z_v(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) { - return 0x0000007d; + return 0x0000007dU; } static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) { - return 0x0000007e; + return 0x0000007eU; } static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) { - return 0x0000007f; + return 0x0000007fU; } static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gmmu_pte_kind_zf32_2cs_v(void) { - return 0x00000081; + return 0x00000081U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) { - return 0x00000082; + return 0x00000082U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) { - return 0x00000083; + return 0x00000083U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) { - return 0x00000085; + return 0x00000085U; } static inline u32 gmmu_pte_kind_zf32_2cz_v(void) { - return 0x00000086; + return 0x00000086U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) { - return 0x00000087; + return 0x00000087U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) { - return 0x00000088; + return 0x00000088U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) { - return 0x00000089; + return 0x00000089U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) { - return 0x0000008a; + return 0x0000008aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) { - return 0x0000008b; + return 0x0000008bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) { - return 0x0000008c; + return 0x0000008cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) { - return 0x0000008d; + return 0x0000008dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) { - return 0x0000008e; + return 0x0000008eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x0000008f; + return 0x0000008fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x00000090; + return 0x00000090U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x00000091; + return 0x00000091U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x00000092; + return 0x00000092U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x00000097; + return 0x00000097U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x00000098; + return 0x00000098U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x00000099; + return 0x00000099U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x0000009a; + return 0x0000009aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x0000009b; + return 0x0000009bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x0000009c; + return 0x0000009cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x0000009d; + return 0x0000009dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x0000009e; + return 0x0000009eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x0000009f; + return 0x0000009fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000a1; + return 0x000000a1U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000a2; + return 0x000000a2U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000a3; + return 0x000000a3U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000a5; + return 0x000000a5U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000a6; + return 0x000000a6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) { - return 0x000000a7; + return 0x000000a7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) { - return 0x000000a9; + return 0x000000a9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) { - return 0x000000aa; + return 0x000000aaU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x000000ab; + return 0x000000abU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x000000ac; + return 0x000000acU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x000000ad; + return 0x000000adU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x000000ae; + return 0x000000aeU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x000000b3; + return 0x000000b3U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x000000b4; + return 0x000000b4U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x000000b5; + return 0x000000b5U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x000000b6; + return 0x000000b6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x000000b7; + return 0x000000b7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x000000b9; + return 0x000000b9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x000000ba; + return 0x000000baU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x000000bb; + return 0x000000bbU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000bd; + return 0x000000bdU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000be; + return 0x000000beU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000bf; + return 0x000000bfU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000c1; + return 0x000000c1U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000c2; + return 0x000000c2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) { - return 0x000000c3; + return 0x000000c3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) { - return 0x000000c5; + return 0x000000c5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) { - return 0x000000c6; + return 0x000000c6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) { - return 0x000000c7; + return 0x000000c7U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) { - return 0x000000ce; + return 0x000000ceU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) { - return 0x000000cf; + return 0x000000cfU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) { - return 0x000000d1; + return 0x000000d1U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) { - return 0x000000d2; + return 0x000000d2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) { - return 0x000000d3; + return 0x000000d3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) { - return 0x000000d5; + return 0x000000d5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) { - return 0x000000d6; + return 0x000000d6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) { - return 0x000000d7; + return 0x000000d7U; } static inline u32 gmmu_pte_kind_generic_16bx2_v(void) { - return 0x000000fe; + return 0x000000feU; } static inline u32 gmmu_pte_kind_c32_2c_v(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 gmmu_pte_kind_c32_2cbr_v(void) { - return 0x000000d9; + return 0x000000d9U; } static inline u32 gmmu_pte_kind_c32_2cba_v(void) { - return 0x000000da; + return 0x000000daU; } static inline u32 gmmu_pte_kind_c32_2cra_v(void) { - return 0x000000db; + return 0x000000dbU; } static inline u32 gmmu_pte_kind_c32_2bra_v(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) { - return 0x000000dd; + return 0x000000ddU; } static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) { - return 0x000000de; + return 0x000000deU; } static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) { - return 0x000000df; + return 0x000000dfU; } static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) { - return 0x000000e1; + return 0x000000e1U; } static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) { - return 0x000000e2; + return 0x000000e2U; } static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) { - return 0x000000e3; + return 0x000000e3U; } static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) { - return 0x000000e5; + return 0x000000e5U; } static inline u32 gmmu_pte_kind_c64_2c_v(void) { - return 0x000000e6; + return 0x000000e6U; } static inline u32 gmmu_pte_kind_c64_2cbr_v(void) { - return 0x000000e7; + return 0x000000e7U; } static inline u32 gmmu_pte_kind_c64_2cba_v(void) { - return 0x000000e8; + return 0x000000e8U; } static inline u32 gmmu_pte_kind_c64_2cra_v(void) { - return 0x000000e9; + return 0x000000e9U; } static inline u32 gmmu_pte_kind_c64_2bra_v(void) { - return 0x000000ea; + return 0x000000eaU; } static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) { - return 0x000000eb; + return 0x000000ebU; } static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) { - return 0x000000cd; + return 0x000000cdU; } static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) { - return 0x000000ed; + return 0x000000edU; } static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) { - return 0x000000ee; + return 0x000000eeU; } static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) { - return 0x000000ef; + return 0x000000efU; } static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) { - return 0x000000f1; + return 0x000000f1U; } static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) { - return 0x0000002d; + return 0x0000002dU; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) { - return 0x000000f2; + return 0x000000f2U; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) { - return 0x000000f3; + return 0x000000f3U; } static inline u32 gmmu_pte_kind_c128_2c_v(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 gmmu_pte_kind_c128_2cr_v(void) { - return 0x000000f5; + return 0x000000f5U; } static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) { - return 0x000000f6; + return 0x000000f6U; } static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) { - return 0x000000f7; + return 0x000000f7U; } static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) { - return 0x000000f9; + return 0x000000f9U; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) { - return 0x000000fa; + return 0x000000faU; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) { - return 0x000000fb; + return 0x000000fbU; } static inline u32 gmmu_pte_kind_x8c24_v(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) { - return 0x000000fd; + return 0x000000fdU; } static inline u32 gmmu_pte_kind_smsked_message_v(void) { - return 0x000000ca; + return 0x000000caU; } static inline u32 gmmu_pte_kind_smhost_message_v(void) { - return 0x000000cb; + return 0x000000cbU; } static inline u32 gmmu_pte_kind_s8_v(void) { - return 0x0000002a; + return 0x0000002aU; } static inline u32 gmmu_pte_kind_s8_2s_v(void) { - return 0x0000002b; + return 0x0000002bU; } static inline u32 gmmu_fault_client_type_gpc_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_fault_client_type_hub_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_type_unbound_inst_block_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 gmmu_fault_buf_size_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) { - return (r >> 8) & 0x3; + return (r >> 8U) & 0x3U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) { - return 0; + return 0U; } static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) { - return 1; + return 1U; } static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) { - return 2; + return 2U; } static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) { - return 2; + return 2U; } static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) { - return 3; + return 3U; } static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) { - return 4; + return 4U; } static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) { - return 5; + return 5U; } static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 gmmu_fault_buf_entry_engine_id_w(void) { - return 6; + return 6U; } static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gmmu_fault_buf_entry_fault_type_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) { - return 0x80; + return 0x80U; } static inline u32 gmmu_fault_buf_entry_client_v(u32 r) { - return (r >> 8) & 0x7f; + return (r >> 8U) & 0x7fU; } static inline u32 gmmu_fault_buf_entry_client_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 gmmu_fault_buf_entry_access_type_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gmmu_fault_buf_entry_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_valid_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 1af014f6..3bdf2de2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -58,4858 +58,4858 @@ static inline u32 gr_intr_r(void) { - return 0x00400100; + return 0x00400100U; } static inline u32 gr_intr_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_notify_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_semaphore_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_semaphore_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_illegal_method_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_method_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_notify_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_illegal_notify_reset_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_firmware_method_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_intr_firmware_method_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_firmware_method_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_illegal_class_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_illegal_class_reset_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_fecs_error_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_fecs_error_reset_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_class_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_class_error_reset_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_exception_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_intr_exception_reset_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_fecs_intr_r(void) { - return 0x00400144; + return 0x00400144U; } static inline u32 gr_class_error_r(void) { - return 0x00400110; + return 0x00400110U; } static inline u32 gr_class_error_code_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_intr_nonstall_r(void) { - return 0x00400120; + return 0x00400120U; } static inline u32 gr_intr_nonstall_trap_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_en_r(void) { - return 0x0040013c; + return 0x0040013cU; } static inline u32 gr_exception_r(void) { - return 0x00400108; + return 0x00400108U; } static inline u32 gr_exception_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_sked_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_exception1_r(void) { - return 0x00400118; + return 0x00400118U; } static inline u32 gr_exception1_gpc_0_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception2_r(void) { - return 0x0040011c; + return 0x0040011cU; } static inline u32 gr_exception_en_r(void) { - return 0x00400138; + return 0x00400138U; } static inline u32 gr_exception_en_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_en_fe_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception_en_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_en_gpc_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 gr_exception_en_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_en_memfmt_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_exception_en_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_en_ds_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_exception1_en_r(void) { - return 0x00400130; + return 0x00400130U; } static inline u32 gr_exception2_en_r(void) { - return 0x00400134; + return 0x00400134U; } static inline u32 gr_gpfifo_ctl_r(void) { - return 0x00400500; + return 0x00400500U; } static inline u32 gr_gpfifo_ctl_access_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpfifo_ctl_access_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpfifo_ctl_access_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpfifo_status_r(void) { - return 0x00400504; + return 0x00400504U; } static inline u32 gr_trapped_addr_r(void) { - return 0x00400704; + return 0x00400704U; } static inline u32 gr_trapped_addr_mthd_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 gr_trapped_addr_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 gr_trapped_data_lo_r(void) { - return 0x00400708; + return 0x00400708U; } static inline u32 gr_trapped_data_hi_r(void) { - return 0x0040070c; + return 0x0040070cU; } static inline u32 gr_status_r(void) { - return 0x00400700; + return 0x00400700U; } static inline u32 gr_status_fe_method_upper_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_status_fe_method_lower_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_status_fe_method_lower_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_status_fe_gi_v(u32 r) { - return (r >> 21) & 0x1; + return (r >> 21U) & 0x1U; } static inline u32 gr_status_mask_r(void) { - return 0x00400610; + return 0x00400610U; } static inline u32 gr_status_1_r(void) { - return 0x00400604; + return 0x00400604U; } static inline u32 gr_status_2_r(void) { - return 0x00400608; + return 0x00400608U; } static inline u32 gr_engine_status_r(void) { - return 0x0040060c; + return 0x0040060cU; } static inline u32 gr_engine_status_value_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_be0_becs_be_exception_r(void) { - return 0x00410204; + return 0x00410204U; } static inline u32 gr_pri_be0_becs_be_exception_en_r(void) { - return 0x00410208; + return 0x00410208U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) { - return 0x00502c94; + return 0x00502c94U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_activity_0_r(void) { - return 0x00400380; + return 0x00400380U; } static inline u32 gr_activity_1_r(void) { - return 0x00400384; + return 0x00400384U; } static inline u32 gr_activity_2_r(void) { - return 0x00400388; + return 0x00400388U; } static inline u32 gr_activity_4_r(void) { - return 0x00400390; + return 0x00400390U; } static inline u32 gr_activity_4_gpc0_s(void) { - return 3; + return 3U; } static inline u32 gr_activity_4_gpc0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_activity_4_gpc0_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 gr_activity_4_gpc0_v(u32 r) { - return (r >> 0) & 0x7; + return (r >> 0U) & 0x7U; } static inline u32 gr_activity_4_gpc0_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_activity_4_gpc0_preempted_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pri_gpc0_gcc_dbg_r(void) { - return 0x00501000; + return 0x00501000U; } static inline u32 gr_pri_gpcs_gcc_dbg_r(void) { - return 0x00419000; + return 0x00419000U; } static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { - return 0x0050433c; + return 0x0050433cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) { - return 0x00419b3c; + return 0x00419b3cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_sked_activity_r(void) { - return 0x00407054; + return 0x00407054U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) { - return 0x00502c80; + return 0x00502c80U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) { - return 0x00502c84; + return 0x00502c84U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) { - return 0x00502c88; + return 0x00502c88U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) { - return 0x00502c8c; + return 0x00502c8cU; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x00504500; + return 0x00504500U; } static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x00504d00; + return 0x00504d00U; } static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00501d00; + return 0x00501d00U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) { - return 0x0041ac80; + return 0x0041ac80U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) { - return 0x0041ac84; + return 0x0041ac84U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) { - return 0x0041ac88; + return 0x0041ac88U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) { - return 0x0041ac8c; + return 0x0041ac8cU; } static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x0041c500; + return 0x0041c500U; } static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x0041cd00; + return 0x0041cd00U; } static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00419d00; + return 0x00419d00U; } static inline u32 gr_pri_be0_becs_be_activity0_r(void) { - return 0x00410200; + return 0x00410200U; } static inline u32 gr_pri_be1_becs_be_activity0_r(void) { - return 0x00410600; + return 0x00410600U; } static inline u32 gr_pri_bes_becs_be_activity0_r(void) { - return 0x00408a00; + return 0x00408a00U; } static inline u32 gr_pri_ds_mpipe_status_r(void) { - return 0x00405858; + return 0x00405858U; } static inline u32 gr_pri_fe_go_idle_info_r(void) { - return 0x00404194; + return 0x00404194U; } static inline u32 gr_pri_fe_chip_def_info_r(void) { - return 0x00404030; + return 0x00404030U; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { - return 0x00504238; + return 0x00504238U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { - return 0x00504358; + return 0x00504358U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 26) & 0x1; + return (r >> 26U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) { - return 0x0050435c; + return 0x0050435cU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) { - return 0x00504360; + return 0x00504360U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) { - return 0x0050436c; + return 0x0050436cU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) { - return 0x00504370; + return 0x00504370U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) { - return 0x00504374; + return 0x00504374U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) { - return 0x0050464c; + return 0x0050464cU; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 18) & 0x1; + return (r >> 18U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) { - return 0x00504650; + return 0x00504650U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) { - return 0x00504654; + return 0x00504654U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) { - return 0x00504624; + return 0x00504624U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) { - return 0x00504628; + return 0x00504628U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) { - return 0x0050462c; + return 0x0050462cU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) { - return 0x00504638; + return 0x00504638U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 18) & 0x1; + return (r >> 18U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) { - return 0x0050463c; + return 0x0050463cU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) { - return 0x00504640; + return 0x00504640U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { - return 0x005042c4; + return 0x005042c4U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) { - return 0x00504430; + return 0x00504430U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) { - return 0x00504434; + return 0x00504434U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_pri_be0_crop_status1_r(void) { - return 0x00410134; + return 0x00410134U; } static inline u32 gr_pri_bes_crop_status1_r(void) { - return 0x00408934; + return 0x00408934U; } static inline u32 gr_pri_be0_zrop_status_r(void) { - return 0x00410048; + return 0x00410048U; } static inline u32 gr_pri_be0_zrop_status2_r(void) { - return 0x0041004c; + return 0x0041004cU; } static inline u32 gr_pri_bes_zrop_status_r(void) { - return 0x00408848; + return 0x00408848U; } static inline u32 gr_pri_bes_zrop_status2_r(void) { - return 0x0040884c; + return 0x0040884cU; } static inline u32 gr_pipe_bundle_address_r(void) { - return 0x00400200; + return 0x00400200U; } static inline u32 gr_pipe_bundle_address_value_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pipe_bundle_address_veid_f(u32 v) { - return (v & 0x3f) << 20; + return (v & 0x3fU) << 20U; } static inline u32 gr_pipe_bundle_address_veid_w(void) { - return 0; + return 0U; } static inline u32 gr_pipe_bundle_data_r(void) { - return 0x00400204; + return 0x00400204U; } static inline u32 gr_pipe_bundle_config_r(void) { - return 0x00400208; + return 0x00400208U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fe_hww_esr_r(void) { - return 0x00404000; + return 0x00404000U; } static inline u32 gr_fe_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_fe_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { - return 0x00419eac; + return 0x00419eacU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) { - return 0x0050472c; + return 0x0050472cU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) { - return 0x00419eb4; + return 0x00419eb4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) { - return 0x00504734; + return 0x00504734U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fe_go_idle_timeout_r(void) { - return 0x00404154; + return 0x00404154U; } static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) { - return 0x1800; + return 0x1800U; } static inline u32 gr_fe_object_table_r(u32 i) { - return 0x00404200 + i*4; + return 0x00404200U + i*4U; } static inline u32 gr_fe_object_table_nvclass_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fe_tpc_fs_r(u32 i) { - return 0x0040a200 + i*4; + return 0x0040a200U + i*4U; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { - return 0x00404488; + return 0x00404488U; } static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pri_mme_shadow_raw_data_r(void) { - return 0x0040448c; + return 0x0040448cU; } static inline u32 gr_mme_hww_esr_r(void) { - return 0x00404490; + return 0x00404490U; } static inline u32 gr_mme_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_mme_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_memfmt_hww_esr_r(void) { - return 0x00404600; + return 0x00404600U; } static inline u32 gr_memfmt_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_memfmt_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fecs_cpuctl_r(void) { - return 0x00409100; + return 0x00409100U; } static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_cpuctl_alias_r(void) { - return 0x00409130; + return 0x00409130U; } static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_dmactl_r(void) { - return 0x0040910c; + return 0x0040910cU; } static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_fecs_os_r(void) { - return 0x00409080; + return 0x00409080U; } static inline u32 gr_fecs_idlestate_r(void) { - return 0x0040904c; + return 0x0040904cU; } static inline u32 gr_fecs_mailbox0_r(void) { - return 0x00409040; + return 0x00409040U; } static inline u32 gr_fecs_mailbox1_r(void) { - return 0x00409044; + return 0x00409044U; } static inline u32 gr_fecs_irqstat_r(void) { - return 0x00409008; + return 0x00409008U; } static inline u32 gr_fecs_irqmode_r(void) { - return 0x0040900c; + return 0x0040900cU; } static inline u32 gr_fecs_irqmask_r(void) { - return 0x00409018; + return 0x00409018U; } static inline u32 gr_fecs_irqdest_r(void) { - return 0x0040901c; + return 0x0040901cU; } static inline u32 gr_fecs_curctx_r(void) { - return 0x00409050; + return 0x00409050U; } static inline u32 gr_fecs_nxtctx_r(void) { - return 0x00409054; + return 0x00409054U; } static inline u32 gr_fecs_engctl_r(void) { - return 0x004090a4; + return 0x004090a4U; } static inline u32 gr_fecs_debug1_r(void) { - return 0x00409090; + return 0x00409090U; } static inline u32 gr_fecs_debuginfo_r(void) { - return 0x00409094; + return 0x00409094U; } static inline u32 gr_fecs_icd_cmd_r(void) { - return 0x00409200; + return 0x00409200U; } static inline u32 gr_fecs_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_fecs_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 gr_fecs_icd_rdata_r(void) { - return 0x0040920c; + return 0x0040920cU; } static inline u32 gr_fecs_imemc_r(u32 i) { - return 0x00409180 + i*16; + return 0x00409180U + i*16U; } static inline u32 gr_fecs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_imemd_r(u32 i) { - return 0x00409184 + i*16; + return 0x00409184U + i*16U; } static inline u32 gr_fecs_imemt_r(u32 i) { - return 0x00409188 + i*16; + return 0x00409188U + i*16U; } static inline u32 gr_fecs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_dmemc_r(u32 i) { - return 0x004091c0 + i*8; + return 0x004091c0U + i*8U; } static inline u32 gr_fecs_dmemc_offs_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 gr_fecs_dmemc_offs_v(u32 r) { - return (r >> 2) & 0x3f; + return (r >> 2U) & 0x3fU; } static inline u32 gr_fecs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_dmemd_r(u32 i) { - return 0x004091c4 + i*8; + return 0x004091c4U + i*8U; } static inline u32 gr_fecs_dmatrfbase_r(void) { - return 0x00409110; + return 0x00409110U; } static inline u32 gr_fecs_dmatrfmoffs_r(void) { - return 0x00409114; + return 0x00409114U; } static inline u32 gr_fecs_dmatrffboffs_r(void) { - return 0x0040911c; + return 0x0040911cU; } static inline u32 gr_fecs_dmatrfcmd_r(void) { - return 0x00409118; + return 0x00409118U; } static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_fecs_bootvec_r(void) { - return 0x00409104; + return 0x00409104U; } static inline u32 gr_fecs_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_falcon_hwcfg_r(void) { - return 0x00409108; + return 0x00409108U; } static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) { - return 0x0041a108; + return 0x0041a108U; } static inline u32 gr_fecs_falcon_rm_r(void) { - return 0x00409084; + return 0x00409084U; } static inline u32 gr_fecs_current_ctx_r(void) { - return 0x00409b00; + return 0x00409b00U; } static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_current_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_current_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_current_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_current_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 gr_fecs_current_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_current_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_current_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_current_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_current_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_method_data_r(void) { - return 0x00409500; + return 0x00409500U; } static inline u32 gr_fecs_method_push_r(void) { - return 0x00409504; + return 0x00409504U; } static inline u32 gr_fecs_method_push_adr_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) { - return 0x3; + return 0x3U; } static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { - return 0x21; + return 0x21U; } static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gr_fecs_host_int_status_r(void) { - return 0x00409c18; + return 0x00409c18U; } static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) { - return 0x1 << 21; + return 0x1U << 21U; } static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) { - return 0x1 << 22; + return 0x1U << 22U; } static inline u32 gr_fecs_host_int_clear_r(void) { - return 0x00409c20; + return 0x00409c20U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_r(void) { - return 0x00409c24; + return 0x00409c24U; } static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) { - return 0x00409614; + return 0x00409614U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) { - return 0x0040960c; + return 0x0040960cU; } static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) { - return 0x00409800 + i*4; + return 0x00409800U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) { - return 0x004098c0 + i*4; + return 0x004098c0U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) { - return 0x00409840 + i*4; + return 0x00409840U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_fs_r(void) { - return 0x00409604; + return 0x00409604U; } static inline u32 gr_fecs_fs_num_available_gpcs_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_fs_num_available_fbps_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_m(void) { - return 0x1f << 16; + return 0x1fU << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_fecs_cfg_r(void) { - return 0x00409620; + return 0x00409620U; } static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_fecs_rc_lanes_r(void) { - return 0x00409880; + return 0x00409880U; } static inline u32 gr_fecs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_fecs_ctxsw_status_1_r(void) { - return 0x00409400; + return 0x00409400U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_adr_r(void) { - return 0x00409a24; + return 0x00409a24U; } static inline u32 gr_fecs_new_ctx_r(void) { - return 0x00409b04; + return 0x00409b04U; } static inline u32 gr_fecs_new_ctx_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_new_ctx_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_new_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_new_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_new_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_new_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_new_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_new_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_new_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_new_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_ptr_r(void) { - return 0x00409a0c; + return 0x00409a0cU; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_arb_ctx_cmd_r(void) { - return 0x00409a10; + return 0x00409a10U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) { - return 0x00409c00; + return 0x00409c00U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) { - return 0x00502c04; + return 0x00502c04U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) { - return 0x00502400; + return 0x00502400U; } static inline u32 gr_fecs_ctxsw_idlestate_r(void) { - return 0x00409420; + return 0x00409420U; } static inline u32 gr_fecs_feature_override_ecc_r(void) { - return 0x00409658; + return 0x00409658U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { - return 0x00502420; + return 0x00502420U; } static inline u32 gr_rstr2d_gpc_map_r(u32 i) { - return 0x0040780c + i*4; + return 0x0040780cU + i*4U; } static inline u32 gr_rstr2d_map_table_cfg_r(void) { - return 0x004078bc; + return 0x004078bcU; } static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_hww_esr_r(void) { - return 0x00406018; + return 0x00406018U; } static inline u32 gr_pd_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pd_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) { - return 0x00406028 + i*4; + return 0x00406028U + i*4U; } static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) { - return (v & 0xf) << 24; + return (v & 0xfU) << 24U; } static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) { - return (v & 0xf) << 28; + return (v & 0xfU) << 28U; } static inline u32 gr_pd_ab_dist_cfg0_r(void) { - return 0x004064c0; + return 0x004064c0U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pd_ab_dist_cfg1_r(void) { - return 0x004064c4; + return 0x004064c4U; } static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) { - return 0xffff; + return 0xffffU; } static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gr_pd_ab_dist_cfg2_r(void) { - return 0x004064c8; + return 0x004064c8U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) { - return (v & 0x1fff) << 0; + return (v & 0x1fffU) << 0U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) { - return 0x00000380; + return 0x00000380U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) { - return (v & 0x1fff) << 16; + return (v & 0x1fffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { - return 0x00000302; + return 0x00000302U; } static inline u32 gr_pd_dist_skip_table_r(u32 i) { - return 0x004064d0 + i*4; + return 0x004064d0U + i*4U; } static inline u32 gr_pd_dist_skip_table__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_ds_debug_r(void) { - return 0x00405800; + return 0x00405800U; } static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 gr_ds_zbc_color_r_r(void) { - return 0x00405804; + return 0x00405804U; } static inline u32 gr_ds_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_g_r(void) { - return 0x00405808; + return 0x00405808U; } static inline u32 gr_ds_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_b_r(void) { - return 0x0040580c; + return 0x0040580cU; } static inline u32 gr_ds_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_a_r(void) { - return 0x00405810; + return 0x00405810U; } static inline u32 gr_ds_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_r(void) { - return 0x00405814; + return 0x00405814U; } static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) { - return (v & 0x7f) << 0; + return (v & 0x7fU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gr_ds_zbc_z_r(void) { - return 0x00405818; + return 0x00405818U; } static inline u32 gr_ds_zbc_z_val_s(void) { - return 32; + return 32U; } static inline u32 gr_ds_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_z_val_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_ds_zbc_z_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_ds_zbc_z_val__init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_ds_zbc_z_val__init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_r(void) { - return 0x0040581c; + return 0x0040581cU; } static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_tbl_index_r(void) { - return 0x00405820; + return 0x00405820U; } static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_ds_zbc_tbl_ld_r(void) { - return 0x00405824; + return 0x00405824U; } static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_tga_constraintlogic_beta_r(void) { - return 0x00405830; + return 0x00405830U; } static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) { - return 0x0040585c; + return 0x0040585cU; } static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_ds_hww_esr_r(void) { - return 0x00405840; + return 0x00405840U; } static inline u32 gr_ds_hww_esr_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_esr_2_r(void) { - return 0x00405848; + return 0x00405848U; } static inline u32 gr_ds_hww_esr_2_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_2_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_2_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_2_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_report_mask_r(void) { - return 0x00405844; + return 0x00405844U; } static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_ds_hww_report_mask_2_r(void) { - return 0x0040584c; + return 0x0040584cU; } static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) { - return 0x00405870 + i*4; + return 0x00405870U + i*4U; } static inline u32 gr_scc_bundle_cb_base_r(void) { - return 0x00408004; + return 0x00408004U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_bundle_cb_size_r(void) { - return 0x00408008; + return 0x00408008U; } static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_pagepool_base_r(void) { - return 0x0040800c; + return 0x0040800cU; } static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_pagepool_r(void) { - return 0x00408010; + return 0x00408010U; } static inline u32 gr_scc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_pagepool_max_valid_pages_s(void) { - return 10; + return 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) { - return (v & 0x3ff) << 10; + return (v & 0x3ffU) << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_m(void) { - return 0x3ff << 10; + return 0x3ffU << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) { - return (r >> 10) & 0x3ff; + return (r >> 10U) & 0x3ffU; } static inline u32 gr_scc_pagepool_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_init_r(void) { - return 0x0040802c; + return 0x0040802cU; } static inline u32 gr_scc_init_ram_trigger_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_scc_hww_esr_r(void) { - return 0x00408030; + return 0x00408030U; } static inline u32 gr_scc_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_scc_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_sked_hww_esr_r(void) { - return 0x00407020; + return 0x00407020U; } static inline u32 gr_sked_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_sked_hww_esr_en_r(void) { - return 0x00407024; + return 0x00407024U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) { - return 0x1 << 25; + return 0x1U << 25U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 gr_cwd_fs_r(void) { - return 0x00405b00; + return 0x00405b00U; } static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) { - return 0x00405b60 + i*4; + return 0x00405b60U + i*4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_cwd_sm_id_r(u32 i) { - return 0x00405ba0 + i*4; + return 0x00405ba0U + i*4U; } static inline u32 gr_cwd_sm_id__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpc0_fs_gpc_r(void) { - return 0x00502608; + return 0x00502608U; } static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_gpc0_cfg_r(void) { - return 0x00502620; + return 0x00502620U; } static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpccs_rc_lanes_r(void) { - return 0x00502880; + return 0x00502880U; } static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_rc_lane_size_r(void) { - return 0x00502910; + return 0x00502910U; } static inline u32 gr_gpccs_rc_lane_size_v_s(void) { - return 24; + return 24U; } static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_zcull_fs_r(void) { - return 0x00500910; + return 0x00500910U; } static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_gpc0_zcull_ram_addr_r(void) { - return 0x00500914; + return 0x00500914U; } static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) { - return 0x00500918; + return 0x00500918U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) { - return 0x00800000; + return 0x00800000U; } static inline u32 gr_gpc0_zcull_total_ram_size_r(void) { - return 0x00500920; + return 0x00500920U; } static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) { - return 0x00500a04 + i*32; + return 0x00500a04U + i*32U; } static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) { - return 0x00500c10 + i*4; + return 0x00500c10U + i*4U; } static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) { - return 0x00500c30 + i*4; + return 0x00500c30U + i*4U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) { - return 0x00504088; + return 0x00504088U; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { - return 0x00504608; + return 0x00504608U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { - return 0x00504330; + return 0x00504330U; } static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) { - return (r >> 8) & 0xfff; + return (r >> 8U) & 0xfffU; } static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) { - return (r >> 20) & 0xfff; + return (r >> 20U) & 0xfffU; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) { - return 0x00503018; + return 0x00503018U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) { - return 0x005030c0; + return 0x005030c0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00001100; + return 0x00001100U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) { - return 0x005030f4; + return 0x005030f4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) { - return 0x005030e4; + return 0x005030e4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) { - return 0x005030f8; + return 0x005030f8U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) { - return 0x005030f0; + return 0x005030f0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { - return 0x00419e00; + return 0x00419e00U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) { - return 0x00419e04; + return 0x00419e04U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) { - return 21; + return 21U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) { - return (v & 0x1fffff) << 0; + return (v & 0x1fffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) { - return 0x1fffff << 0; + return 0x1fffffU << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) { - return (r >> 0) & 0x1fffff; + return (r >> 0U) & 0x1fffffU; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpccs_falcon_addr_r(void) { - return 0x0041a0ac; + return 0x0041a0acU; } static inline u32 gr_gpccs_falcon_addr_lsb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_msb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) { - return (r >> 6) & 0x3f; + return (r >> 6U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_ext_s(void) { - return 12; + return 12U; } static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_m(void) { - return 0xfff << 0; + return 0xfffU << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_gpccs_cpuctl_r(void) { - return 0x0041a100; + return 0x0041a100U; } static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpccs_dmactl_r(void) { - return 0x0041a10c; + return 0x0041a10cU; } static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpccs_imemc_r(u32 i) { - return 0x0041a180 + i*16; + return 0x0041a180U + i*16U; } static inline u32 gr_gpccs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_imemd_r(u32 i) { - return 0x0041a184 + i*16; + return 0x0041a184U + i*16U; } static inline u32 gr_gpccs_imemt_r(u32 i) { - return 0x0041a188 + i*16; + return 0x0041a188U + i*16U; } static inline u32 gr_gpccs_imemt__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_gpccs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpccs_dmemc_r(u32 i) { - return 0x0041a1c0 + i*8; + return 0x0041a1c0U + i*8U; } static inline u32 gr_gpccs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_dmemd_r(u32 i) { - return 0x0041a1c4 + i*8; + return 0x0041a1c4U + i*8U; } static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) { - return 0x0041a800 + i*4; + return 0x0041a800U + i*4U; } static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) { - return 0x00418e24; + return 0x00418e24U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) { - return 32; + return 32U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) { - return 0x00418e28; + return 0x00418e28U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) { - return 11; + return 11U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) { - return 0x7ff << 0; + return 0x7ffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) { - return (r >> 0) & 0x7ff; + return (r >> 0U) & 0x7ffU; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) { - return 0x30; + return 0x30U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) { - return 0x005001dc; + return 0x005001dcU; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { - return 0x00000170; + return 0x00000170U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { - return 0x005001d8; + return 0x005001d8U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) { - return 0x004181e4; + return 0x004181e4U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) { - return 0x0041befc; + return 0x0041befcU; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) { - return 0x00418ea0 + i*4; + return 0x00418ea0U + i*4U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) { - return 0x00418010 + i*4; + return 0x00418010U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) { - return 0x0041804c + i*4; + return 0x0041804cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) { - return 0x00418088 + i*4; + return 0x00418088U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) { - return 0x004180c4 + i*4; + return 0x004180c4U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) { - return 0x00418100; + return 0x00418100U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) { - return 0x00418110 + i*4; + return 0x00418110U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) { - return 0x0041814c; + return 0x0041814cU; } static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) { - return 0x0041815c + i*4; + return 0x0041815cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) { - return 0x00418198; + return 0x00418198U; } static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { - return 0x00418810; + return 0x00418810U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_crstr_gpc_map_r(u32 i) { - return 0x00418b08 + i*4; + return 0x00418b08U + i*4U; } static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) { - return (v & 0x1f) << 5; + return (v & 0x1fU) << 5U; } static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) { - return (v & 0x1f) << 10; + return (v & 0x1fU) << 10U; } static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) { - return (v & 0x1f) << 20; + return (v & 0x1fU) << 20U; } static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) { - return (v & 0x1f) << 25; + return (v & 0x1fU) << 25U; } static inline u32 gr_crstr_map_table_cfg_r(void) { - return 0x00418bb8; + return 0x00418bb8U; } static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) { - return 0x00418980 + i*4; + return 0x00418980U + i*4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) { - return (v & 0x7) << 4; + return (v & 0x7U) << 4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) { - return (v & 0x7) << 16; + return (v & 0x7U) << 16U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x7U) << 20U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) { - return (v & 0x7) << 28; + return (v & 0x7U) << 28U; } static inline u32 gr_gpcs_gpm_pd_cfg_r(void) { - return 0x00418c6c; + return 0x00418c6cU; } static inline u32 gr_gpcs_gcc_pagepool_base_r(void) { - return 0x00419004; + return 0x00419004U; } static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_gcc_pagepool_r(void) { - return 0x00419008; + return 0x00419008U; } static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) { - return 0x0041980c; + return 0x0041980cU; } static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) { - return 0x00419848; + return 0x00419848U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) { - return 0x00419c00; + return 0x00419c00U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) { - return 0x00419c2c; + return 0x00419c2cU; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419ea8; + return 0x00419ea8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) { - return 0x00504728; + return 0x00504728U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { - return 0x00419d0c; + return 0x00419d0cU; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { - return 0x0041ac94; + return 0x0041ac94U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) { - return 0x00501048; + return 0x00501048U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) { - return 0x0050104c; + return 0x0050104cU; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) { - return 0x00501054; + return 0x00501054U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { - return 0x00504704; + return 0x00504704U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) { - return 0x00504708; + return 0x00504708U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) { - return 0x0050470c; + return 0x0050470cU; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) { - return 0x00504710; + return 0x00504710U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) { - return 0x00504714; + return 0x00504714U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) { - return 0x00504718; + return 0x00504718U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) { - return 0x0050471c; + return 0x0050471cU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) { - return 0x00419e90; + return 0x00419e90U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) { - return 0x00419e94; + return 0x00419e94U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) { - return 0x00419e80; + return 0x00419e80U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { - return 0x00504700; + return 0x00504700U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { - return 0x00504730; + return 0x00504730U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) { - return 0xf << 24; + return 0xfU << 24U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) { - return 0x0050460c; + return 0x0050460cU; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { - return 0x00504738; + return 0x00504738U; } static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { - return 0x005043a0; + return 0x005043a0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) { - return 0x00419ba0; + return 0x00419ba0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) { - return 0x005043b0; + return 0x005043b0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) { - return 0x00419bb0; + return 0x00419bb0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) { - return 0x0041be08; + return 0x0041be08U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) { - return 0x0041bf00 + i*4; + return 0x0041bf00U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { - return 0x0041bfd0; + return 0x0041bfd0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) { - return (v & 0x7) << 21; + return (v & 0x7U) << 21U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) { - return 0x0041bfd4; + return 0x0041bfd4U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) { - return 0x0041bfb0 + i*4; + return 0x0041bfb0U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_bes_zrop_settings_r(void) { - return 0x00408850; + return 0x00408850U; } static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_be0_crop_debug3_r(void) { - return 0x00410108; + return 0x00410108U; } static inline u32 gr_bes_crop_debug3_r(void) { - return 0x00408908; + return 0x00408908U; } static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_bes_crop_settings_r(void) { - return 0x00408958; + return 0x00408958U; } static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gr_zcull_subregion_qty_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) { - return 0x00419a00; + return 0x00419a00U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) { - return 0x00419bf0; + return 0x00419bf0U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) { - return 0x00584200; + return 0x00584200U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) { - return 0x00584204; + return 0x00584204U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) { - return 0x00584208; + return 0x00584208U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) { - return 0x00584210; + return 0x00584210U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) { - return 0x00584214; + return 0x00584214U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) { - return 0x00584218; + return 0x00584218U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) { - return 0x0058421c; + return 0x0058421cU; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) { - return 0x0058420c; + return 0x0058420cU; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) { - return 0x00584220; + return 0x00584220U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) { - return 0x00584224; + return 0x00584224U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) { - return 0x00584228; + return 0x00584228U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) { - return 0x0058422c; + return 0x0058422cU; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) { - return 0x00584230; + return 0x00584230U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) { - return 0x00584234; + return 0x00584234U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) { - return 0x00584238; + return 0x00584238U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) { - return 0x0058423c; + return 0x0058423cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) { - return 0x00584600; + return 0x00584600U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) { - return 0x00584604; + return 0x00584604U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) { - return 0x00584624; + return 0x00584624U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) { - return 0x00584628; + return 0x00584628U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) { - return 0x0058462c; + return 0x0058462cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) { - return 0x00584630; + return 0x00584630U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) { - return 0x00584634; + return 0x00584634U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) { - return 0x00584638; + return 0x00584638U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) { - return 0x0058463c; + return 0x0058463cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) { - return 0x00584640; + return 0x00584640U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) { - return 0x00584644; + return 0x00584644U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) { - return 0x00584648; + return 0x00584648U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) { - return 0x0058464c; + return 0x0058464cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) { - return 0x00584650; + return 0x00584650U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) { - return 0x00584654; + return 0x00584654U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) { - return 0x00584658; + return 0x00584658U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) { - return 0x0058465c; + return 0x0058465cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) { - return 0x00584660; + return 0x00584660U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) { - return 0x00584614; + return 0x00584614U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) { - return 0x00584618; + return 0x00584618U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) { - return 0x0058461c; + return 0x0058461cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) { - return 0x00584620; + return 0x00584620U; } static inline u32 gr_fe_pwr_mode_r(void) { - return 0x00404170; + return 0x00404170U; } static inline u32 gr_fe_pwr_mode_mode_auto_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fe_pwr_mode_req_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_fe_pwr_mode_req_send_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fe_pwr_mode_req_done_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) { - return 0x00418880; + return 0x00418880U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) { - return 0x3 << 3; + return 0x3U << 3U; } static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) { - return 0x3 << 5; + return 0x3U << 5U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { - return 0x00418890; + return 0x00418890U; } static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) { - return 0x00418894; + return 0x00418894U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) { - return 0x004188b0; + return 0x004188b0U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) { - return 0x004188b4; + return 0x004188b4U; } static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) { - return 0x004188b8; + return 0x004188b8U; } static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { - return 0x004188ac; + return 0x004188acU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419e84; + return 0x00419e84U; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { - return 0x004041c0; + return 0x004041c0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) { - return 0x00419bd8; + return 0x00419bd8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) { - return 0x7 << 8; + return 0x7U << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) { - return 0x00419ba4; + return 0x00419ba4U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { - return 0x3 << 11; + return 0x3U << 11U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_gpcs_tc_debug0_r(void) { - return 0x00418708; + return 0x00418708U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0x1ff << 0; + return 0x1ffU << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) { - return 0x00500324; + return 0x00500324U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) { - return 0x00500314; + return 0x00500314U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 17; + return 0x1U << 17U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) { - return 0x00500320; + return 0x00500320U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) { - return 0x00500318; + return 0x00500318U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) { - return 0x0050031c; + return 0x0050031cU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_hww_esr_r(void) { - return 0x00502c98; + return 0x00502c98U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) { - return 0x00502678; + return 0x00502678U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) { - return 0x00502684; + return 0x00502684U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) { - return (v & 0x7fffff) << 0; + return (v & 0x7fffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) { - return 20; + return 20U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) { - return 0x0050267c; + return 0x0050267cU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) { - return 0x00502680; + return 0x00502680U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_status_r(void) { - return 0x00409678; + return 0x00409678U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fecs_falcon_ecc_address_r(void) { - return 0x00409684; + return 0x00409684U; } static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) { - return (v & 0x7fffff) << 0; + return (v & 0x7fffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) { - return 20; + return 20U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) { - return 0x0040967c; + return 0x0040967cU; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) { - return 0x00409680; + return 0x00409680U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index e1b0f47a..769bcf0c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -58,746 +58,746 @@ static inline u32 ltc_pltcg_base_v(void) { - return 0x00140000; + return 0x00140000U; } static inline u32 ltc_pltcg_extent_v(void) { - return 0x0017ffff; + return 0x0017ffffU; } static inline u32 ltc_ltc0_ltss_v(void) { - return 0x00140200; + return 0x00140200U; } static inline u32 ltc_ltc0_lts0_v(void) { - return 0x00140400; + return 0x00140400U; } static inline u32 ltc_ltcs_ltss_v(void) { - return 0x0017e200; + return 0x0017e200U; } static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) { - return 0x00140518; + return 0x00140518U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) { - return 0x0017e318; + return 0x0017e318U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) { - return 0x00140494; + return 0x00140494U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) { - return (r >> 16) & 0x3; + return (r >> 16U) & 0x3U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) { - return 0x0017e26c; + return 0x0017e26cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) { - return 0x2; + return 0x2U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) { - return 0x0017e270; + return 0x0017e270U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { - return 0x0017e274; + return 0x0017e274U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { - return 0x0003ffff; + return 0x0003ffffU; } static inline u32 ltc_ltcs_ltss_cbc_base_r(void) { - return 0x0017e278; + return 0x0017e278U; } static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) { - return (r >> 0) & 0x3ffffff; + return (r >> 0U) & 0x3ffffffU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { - return 0x0017e27c; + return 0x0017e27cU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) { - return (r >> 25) & 0x1; + return (r >> 25U) & 0x1U; } static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { - return 0x0017e000; + return 0x0017e000U; } static inline u32 ltc_ltcs_ltss_cbc_param_r(void) { - return 0x0017e280; + return 0x0017e280U; } static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) { - return (r >> 28) & 0xf; + return (r >> 28U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) { - return 0x0017e3f4; + return 0x0017e3f4U; } static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) { - return 0x0017e2ac; + return 0x0017e2acU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) { - return 0x0017e338; + return 0x0017e338U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) { - return 0x0017e33c + i*4; + return 0x0017e33cU + i*4U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) { - return 0x0017e34c; + return 0x0017e34cU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) { - return 32; + return 32U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) { - return 0x0017e204; + return 0x0017e204U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) { - return 8; + return 8U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) { - return 0x0017e2b0; + return 0x0017e2b0U; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_g_elpg_r(void) { - return 0x0017e214; + return 0x0017e214U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_r(void) { - return 0x00140214; + return 0x00140214U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_r(void) { - return 0x00142214; + return 0x00142214U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_intr_r(void) { - return 0x0017e20c; + return 0x0017e20cU; } static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 ltc_ltc0_lts0_intr_r(void) { - return 0x0014040c; + return 0x0014040cU; } static inline u32 ltc_ltcs_ltss_intr3_r(void) { - return 0x0017e388; + return 0x0017e388U; } static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 ltc_ltc0_lts0_intr3_r(void) { - return 0x00140588; + return 0x00140588U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) { - return 0x001404f0; + return 0x001404f0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 17; + return 0x1U << 17U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) { - return 0x001404fc; + return 0x001404fcU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) { - return 0x001404f4; + return 0x001404f4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) { - return 0x001404f8; + return 0x001404f8U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) { - return 0x0014051c; + return 0x0014051cU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) { - return 0x0017e2a0; + return 0x0017e2a0U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) { - return 0x0017e2a4; + return 0x0017e2a4U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) { - return 0x001402a0; + return 0x001402a0U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) { - return 0x001402a4; + return 0x001402a4U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) { - return 0x001422a0; + return 0x001422a0U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) { - return 0x001422a4; + return 0x001422a4U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) { - return 0x0014058c; + return 0x0014058cU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 7228cd8b..bff73076 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -58,194 +58,194 @@ static inline u32 mc_boot_0_r(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_boot_0_architecture_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 mc_boot_0_implementation_v(u32 r) { - return (r >> 20) & 0xf; + return (r >> 20U) & 0xfU; } static inline u32 mc_boot_0_major_revision_v(u32 r) { - return (r >> 4) & 0xf; + return (r >> 4U) & 0xfU; } static inline u32 mc_boot_0_minor_revision_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 mc_intr_r(u32 i) { - return 0x00000100 + i*4; + return 0x00000100U + i*4U; } static inline u32 mc_intr_pfifo_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_intr_hub_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 mc_intr_pgraph_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_intr_pmu_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 mc_intr_ltc_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 mc_intr_priv_ring_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 mc_intr_pbus_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_intr_en_r(u32 i) { - return 0x00000140 + i*4; + return 0x00000140U + i*4U; } static inline u32 mc_intr_en_set_r(u32 i) { - return 0x00000160 + i*4; + return 0x00000160U + i*4U; } static inline u32 mc_intr_en_clear_r(u32 i) { - return 0x00000180 + i*4; + return 0x00000180U + i*4U; } static inline u32 mc_enable_r(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 mc_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 mc_enable_pmedia_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pmedia_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 mc_enable_pmedia_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 mc_enable_pmedia_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 mc_enable_ce0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 mc_enable_pfifo_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_enable_pgraph_enabled_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_enable_pwr_v(u32 r) { - return (r >> 13) & 0x1; + return (r >> 13U) & 0x1U; } static inline u32 mc_enable_pwr_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_enable_pwr_enabled_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 mc_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_enable_ce2_m(void) { - return 0x1 << 21; + return 0x1U << 21U; } static inline u32 mc_enable_ce2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 mc_enable_blg_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 mc_enable_perfmon_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_intr_ltc_r(void) { - return 0x000001c0; + return 0x000001c0U; } static inline u32 mc_enable_pb_r(void) { - return 0x00000204; + return 0x00000204U; } static inline u32 mc_enable_pb_0_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pb_0_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 mc_enable_pb_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 mc_enable_pb_0_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 mc_enable_pb_0_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 mc_elpg_enable_r(void) { - return 0x0000020c; + return 0x0000020cU; } static inline u32 mc_elpg_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_elpg_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_elpg_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_elpg_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 025a7af3..74ff4002 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -58,594 +58,594 @@ static inline u32 pbdma_gp_entry1_r(void) { - return 0x10000004; + return 0x10000004U; } static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pbdma_gp_entry1_length_f(u32 v) { - return (v & 0x1fffff) << 10; + return (v & 0x1fffffU) << 10U; } static inline u32 pbdma_gp_entry1_length_v(u32 r) { - return (r >> 10) & 0x1fffff; + return (r >> 10U) & 0x1fffffU; } static inline u32 pbdma_gp_base_r(u32 i) { - return 0x00040048 + i*8192; + return 0x00040048U + i*8192U; } static inline u32 pbdma_gp_base__size_1_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 pbdma_gp_base_offset_f(u32 v) { - return (v & 0x1fffffff) << 3; + return (v & 0x1fffffffU) << 3U; } static inline u32 pbdma_gp_base_rsvd_s(void) { - return 3; + return 3U; } static inline u32 pbdma_gp_base_hi_r(u32 i) { - return 0x0004004c + i*8192; + return 0x0004004cU + i*8192U; } static inline u32 pbdma_gp_base_hi_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 pbdma_gp_fetch_r(u32 i) { - return 0x00040050 + i*8192; + return 0x00040050U + i*8192U; } static inline u32 pbdma_gp_get_r(u32 i) { - return 0x00040014 + i*8192; + return 0x00040014U + i*8192U; } static inline u32 pbdma_gp_put_r(u32 i) { - return 0x00040000 + i*8192; + return 0x00040000U + i*8192U; } static inline u32 pbdma_pb_fetch_r(u32 i) { - return 0x00040054 + i*8192; + return 0x00040054U + i*8192U; } static inline u32 pbdma_pb_fetch_hi_r(u32 i) { - return 0x00040058 + i*8192; + return 0x00040058U + i*8192U; } static inline u32 pbdma_get_r(u32 i) { - return 0x00040018 + i*8192; + return 0x00040018U + i*8192U; } static inline u32 pbdma_get_hi_r(u32 i) { - return 0x0004001c + i*8192; + return 0x0004001cU + i*8192U; } static inline u32 pbdma_put_r(u32 i) { - return 0x0004005c + i*8192; + return 0x0004005cU + i*8192U; } static inline u32 pbdma_put_hi_r(u32 i) { - return 0x00040060 + i*8192; + return 0x00040060U + i*8192U; } static inline u32 pbdma_pb_header_r(u32 i) { - return 0x00040084 + i*8192; + return 0x00040084U + i*8192U; } static inline u32 pbdma_pb_header_priv_user_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_method_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_subchannel_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_level_main_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_pb_header_type_inc_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_pb_header_type_non_inc_f(void) { - return 0x60000000; + return 0x60000000U; } static inline u32 pbdma_hdr_shadow_r(u32 i) { - return 0x00040118 + i*8192; + return 0x00040118U + i*8192U; } static inline u32 pbdma_subdevice_r(u32 i) { - return 0x00040094 + i*8192; + return 0x00040094U + i*8192U; } static inline u32 pbdma_subdevice_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 pbdma_subdevice_status_active_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_subdevice_channel_dma_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_method0_r(u32 i) { - return 0x000400c0 + i*8192; + return 0x000400c0U + i*8192U; } static inline u32 pbdma_method0_fifo_size_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pbdma_method0_addr_f(u32 v) { - return (v & 0xfff) << 2; + return (v & 0xfffU) << 2U; } static inline u32 pbdma_method0_addr_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 pbdma_method0_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 pbdma_method0_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_method0_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_method1_r(u32 i) { - return 0x000400c8 + i*8192; + return 0x000400c8U + i*8192U; } static inline u32 pbdma_method2_r(u32 i) { - return 0x000400d0 + i*8192; + return 0x000400d0U + i*8192U; } static inline u32 pbdma_method3_r(u32 i) { - return 0x000400d8 + i*8192; + return 0x000400d8U + i*8192U; } static inline u32 pbdma_data0_r(u32 i) { - return 0x000400c4 + i*8192; + return 0x000400c4U + i*8192U; } static inline u32 pbdma_acquire_r(u32 i) { - return 0x00040030 + i*8192; + return 0x00040030U + i*8192U; } static inline u32 pbdma_acquire_retry_man_2_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_acquire_retry_exp_2_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_acquire_timeout_exp_f(u32 v) { - return (v & 0xf) << 11; + return (v & 0xfU) << 11U; } static inline u32 pbdma_acquire_timeout_exp_max_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 pbdma_acquire_timeout_exp_max_f(void) { - return 0x7800; + return 0x7800U; } static inline u32 pbdma_acquire_timeout_man_f(u32 v) { - return (v & 0xffff) << 15; + return (v & 0xffffU) << 15U; } static inline u32 pbdma_acquire_timeout_man_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 pbdma_acquire_timeout_man_max_f(void) { - return 0x7fff8000; + return 0x7fff8000U; } static inline u32 pbdma_acquire_timeout_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_acquire_timeout_en_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_status_r(u32 i) { - return 0x00040100 + i*8192; + return 0x00040100U + i*8192U; } static inline u32 pbdma_channel_r(u32 i) { - return 0x00040120 + i*8192; + return 0x00040120U + i*8192U; } static inline u32 pbdma_signature_r(u32 i) { - return 0x00040010 + i*8192; + return 0x00040010U + i*8192U; } static inline u32 pbdma_signature_hw_valid_f(void) { - return 0xface; + return 0xfaceU; } static inline u32 pbdma_signature_sw_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_r(u32 i) { - return 0x00040008 + i*8192; + return 0x00040008U + i*8192U; } static inline u32 pbdma_userd_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 pbdma_userd_addr_f(u32 v) { - return (v & 0x7fffff) << 9; + return (v & 0x7fffffU) << 9U; } static inline u32 pbdma_config_r(u32 i) { - return 0x000400f4 + i*8192; + return 0x000400f4U + i*8192U; } static inline u32 pbdma_config_l2_evict_first_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_l2_evict_normal_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_config_l2_evict_last_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_config_ce_split_enable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_ce_split_disable_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_config_auth_level_non_privileged_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_auth_level_privileged_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_config_userd_writeback_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_userd_writeback_enable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_userd_hi_r(u32 i) { - return 0x0004000c + i*8192; + return 0x0004000cU + i*8192U; } static inline u32 pbdma_userd_hi_addr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_hce_ctrl_r(u32 i) { - return 0x000400e4 + i*8192; + return 0x000400e4U + i*8192U; } static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_r(u32 i) { - return 0x00040108 + i*8192; + return 0x00040108U + i*8192U; } static inline u32 pbdma_intr_0_memreq_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pbdma_intr_0_memreq_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_intr_0_memack_extra_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_intr_0_memflush_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_memop_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 pbdma_intr_0_lbconnect_pending_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_intr_0_lbreq_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 pbdma_intr_0_lback_extra_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_intr_0_gpfifo_pending_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 pbdma_intr_0_gpptr_pending_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 pbdma_intr_0_gpentry_pending_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 pbdma_intr_0_gpcrc_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_intr_0_pbptr_pending_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_intr_0_pbentry_pending_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 pbdma_intr_0_method_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pbdma_intr_0_methodcrc_pending_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_intr_0_device_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 pbdma_intr_0_eng_reset_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_intr_0_semaphore_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_intr_0_acquire_pending_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 pbdma_intr_0_pri_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_intr_0_pbseg_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 pbdma_intr_0_signature_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_1_r(u32 i) { - return 0x00040148 + i*8192; + return 0x00040148U + i*8192U; } static inline u32 pbdma_intr_1_ctxnotvalid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_en_0_r(u32 i) { - return 0x0004010c + i*8192; + return 0x0004010cU + i*8192U; } static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_en_1_r(u32 i) { - return 0x0004014c + i*8192; + return 0x0004014cU + i*8192U; } static inline u32 pbdma_intr_stall_r(u32 i) { - return 0x0004013c + i*8192; + return 0x0004013cU + i*8192U; } static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_stall_1_r(u32 i) { - return 0x00040140 + i*8192; + return 0x00040140U + i*8192U; } static inline u32 pbdma_udma_nop_r(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pbdma_runlist_timeslice_r(u32 i) { - return 0x000400f8 + i*8192; + return 0x000400f8U + i*8192U; } static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) { - return 0x3000; + return 0x3000U; } static inline u32 pbdma_runlist_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_target_r(u32 i) { - return 0x000400ac + i*8192; + return 0x000400acU + i*8192U; } static inline u32 pbdma_target_engine_sw_f(void) { - return 0x1f; + return 0x1fU; } static inline u32 pbdma_target_eng_ctx_valid_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_target_eng_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_ce_ctx_valid_true_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_target_ce_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 pbdma_target_should_send_tsg_event_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_target_should_send_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_r(u32 i) { - return 0x000400fc + i*8192; + return 0x000400fcU + i*8192U; } static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_set_channel_info_veid_f(u32 v) { - return (v & 0x3f) << 8; + return (v & 0x3fU) << 8U; } static inline u32 pbdma_timeout_r(u32 i) { - return 0x0004012c + i*8192; + return 0x0004012cU + i*8192U; } static inline u32 pbdma_timeout_period_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 pbdma_timeout_period_max_f(void) { - return 0xffffffff; + return 0xffffffffU; } static inline u32 pbdma_timeout_period_init_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h index 5adee5f3..788a6ab6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -58,154 +58,154 @@ static inline u32 perf_pmasys_control_r(void) { - return 0x0024a000; + return 0x0024a000U; } static inline u32 perf_pmasys_control_membuf_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) { - return 0x10; + return 0x10U; } static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) { - return 0x20; + return 0x20U; } static inline u32 perf_pmasys_mem_block_r(void) { - return 0x0024a070; + return 0x0024a070U; } static inline u32 perf_pmasys_mem_block_base_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 perf_pmasys_mem_block_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 perf_pmasys_mem_block_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 perf_pmasys_mem_block_target_lfb_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_target_lfb_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 perf_pmasys_mem_block_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 perf_pmasys_mem_block_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 perf_pmasys_mem_block_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_mem_block_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 perf_pmasys_mem_block_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_outbase_r(void) { - return 0x0024a074; + return 0x0024a074U; } static inline u32 perf_pmasys_outbase_ptr_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_outbaseupper_r(void) { - return 0x0024a078; + return 0x0024a078U; } static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 perf_pmasys_outsize_r(void) { - return 0x0024a07c; + return 0x0024a07cU; } static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_mem_bytes_r(void) { - return 0x0024a084; + return 0x0024a084U; } static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_mem_bump_r(void) { - return 0x0024a088; + return 0x0024a088U; } static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_enginestatus_r(void) { - return 0x0024a0a4; + return 0x0024a0a4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h index 1568f310..456d6316 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -58,6 +58,6 @@ static inline u32 pram_data032_r(u32 i) { - return 0x00700000 + i*4; + return 0x00700000U + i*4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index 24509b08..a653681d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -58,110 +58,110 @@ static inline u32 pri_ringmaster_command_r(void) { - return 0x0012004c; + return 0x0012004cU; } static inline u32 pri_ringmaster_command_cmd_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 pri_ringmaster_command_cmd_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) { - return 0x2; + return 0x2U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) { - return 0x3; + return 0x3U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_command_data_r(void) { - return 0x00120048; + return 0x00120048U; } static inline u32 pri_ringmaster_start_results_r(void) { - return 0x00120050; + return 0x00120050U; } static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pri_ringmaster_intr_status0_r(void) { - return 0x00120058; + return 0x00120058U; } static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 pri_ringmaster_intr_status1_r(void) { - return 0x0012005c; + return 0x0012005cU; } static inline u32 pri_ringmaster_global_ctl_r(void) { - return 0x00120060; + return 0x00120060U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_enum_fbp_r(void) { - return 0x00120074; + return 0x00120074U; } static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_gpc_r(void) { - return 0x00120078; + return 0x00120078U; } static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_ltc_r(void) { - return 0x0012006c; + return 0x0012006cU; } static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index 119e2075..47da22c0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -58,22 +58,22 @@ static inline u32 pri_ringstation_gpc_master_config_r(u32 i) { - return 0x00128300 + i*4; + return 0x00128300U + i*4U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) { - return 0x00128120; + return 0x00128120U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) { - return 0x00128124; + return 0x00128124U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) { - return 0x00128128; + return 0x00128128U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) { - return 0x0012812c; + return 0x0012812cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index 85b86c98..622b6d7b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -58,34 +58,34 @@ static inline u32 pri_ringstation_sys_master_config_r(u32 i) { - return 0x00122300 + i*4; + return 0x00122300U + i*4U; } static inline u32 pri_ringstation_sys_decode_config_r(void) { - return 0x00122204; + return 0x00122204U; } static inline u32 pri_ringstation_sys_decode_config_ring_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringstation_sys_priv_error_adr_r(void) { - return 0x00122120; + return 0x00122120U; } static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) { - return 0x00122124; + return 0x00122124U; } static inline u32 pri_ringstation_sys_priv_error_info_r(void) { - return 0x00122128; + return 0x00122128U; } static inline u32 pri_ringstation_sys_priv_error_code_r(void) { - return 0x0012212c; + return 0x0012212cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 8406ea21..808fe316 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -58,130 +58,130 @@ static inline u32 proj_gpc_base_v(void) { - return 0x00500000; + return 0x00500000U; } static inline u32 proj_gpc_shared_base_v(void) { - return 0x00418000; + return 0x00418000U; } static inline u32 proj_gpc_stride_v(void) { - return 0x00008000; + return 0x00008000U; } static inline u32 proj_ltc_stride_v(void) { - return 0x00002000; + return 0x00002000U; } static inline u32 proj_lts_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_fbpa_stride_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_ppc_in_gpc_base_v(void) { - return 0x00003000; + return 0x00003000U; } static inline u32 proj_ppc_in_gpc_shared_base_v(void) { - return 0x00003e00; + return 0x00003e00U; } static inline u32 proj_ppc_in_gpc_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_rop_base_v(void) { - return 0x00410000; + return 0x00410000U; } static inline u32 proj_rop_shared_base_v(void) { - return 0x00408800; + return 0x00408800U; } static inline u32 proj_rop_stride_v(void) { - return 0x00000400; + return 0x00000400U; } static inline u32 proj_tpc_in_gpc_base_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_tpc_in_gpc_stride_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 proj_tpc_in_gpc_shared_base_v(void) { - return 0x00001800; + return 0x00001800U; } static inline u32 proj_smpc_base_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_smpc_shared_base_v(void) { - return 0x00000300; + return 0x00000300U; } static inline u32 proj_smpc_unique_base_v(void) { - return 0x00000600; + return 0x00000600U; } static inline u32 proj_smpc_stride_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 proj_host_num_engines_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_host_num_pbdma_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 proj_scal_litter_num_gpcs_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_litter_num_zcull_banks_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_max_gpcs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 proj_scal_max_tpc_per_gpc_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 proj_sm_stride_v(void) { - return 0x00000080; + return 0x00000080U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 43c0c908..eba6d806 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -58,894 +58,894 @@ static inline u32 pwr_falcon_irqsset_r(void) { - return 0x0010a000; + return 0x0010a000U; } static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqsclr_r(void) { - return 0x0010a004; + return 0x0010a004U; } static inline u32 pwr_falcon_irqstat_r(void) { - return 0x0010a008; + return 0x0010a008U; } static inline u32 pwr_falcon_irqstat_halt_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 pwr_falcon_irqstat_exterr_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 pwr_falcon_irqmode_r(void) { - return 0x0010a00c; + return 0x0010a00cU; } static inline u32 pwr_falcon_irqmset_r(void) { - return 0x0010a010; + return 0x0010a010U; } static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmset_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmset_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 pwr_falcon_irqmclr_r(void) { - return 0x0010a014; + return 0x0010a014U; } static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 pwr_falcon_irqmask_r(void) { - return 0x0010a018; + return 0x0010a018U; } static inline u32 pwr_falcon_irqdest_r(void) { - return 0x0010a01c; + return 0x0010a01cU; } static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 pwr_falcon_curctx_r(void) { - return 0x0010a050; + return 0x0010a050U; } static inline u32 pwr_falcon_nxtctx_r(void) { - return 0x0010a054; + return 0x0010a054U; } static inline u32 pwr_falcon_mailbox0_r(void) { - return 0x0010a040; + return 0x0010a040U; } static inline u32 pwr_falcon_mailbox1_r(void) { - return 0x0010a044; + return 0x0010a044U; } static inline u32 pwr_falcon_itfen_r(void) { - return 0x0010a048; + return 0x0010a048U; } static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_falcon_idlestate_r(void) { - return 0x0010a04c; + return 0x0010a04cU; } static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) { - return (r >> 1) & 0x7fff; + return (r >> 1U) & 0x7fffU; } static inline u32 pwr_falcon_os_r(void) { - return 0x0010a080; + return 0x0010a080U; } static inline u32 pwr_falcon_engctl_r(void) { - return 0x0010a0a4; + return 0x0010a0a4U; } static inline u32 pwr_falcon_cpuctl_r(void) { - return 0x0010a100; + return 0x0010a100U; } static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_alias_r(void) { - return 0x0010a130; + return 0x0010a130U; } static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_pmu_scpctl_stat_r(void) { - return 0x0010ac08; + return 0x0010ac08U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 pwr_falcon_imemc_r(u32 i) { - return 0x0010a180 + i*16; + return 0x0010a180U + i*16U; } static inline u32 pwr_falcon_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_imemd_r(u32 i) { - return 0x0010a184 + i*16; + return 0x0010a184U + i*16U; } static inline u32 pwr_falcon_imemt_r(u32 i) { - return 0x0010a188 + i*16; + return 0x0010a188U + i*16U; } static inline u32 pwr_falcon_sctl_r(void) { - return 0x0010a240; + return 0x0010a240U; } static inline u32 pwr_falcon_mmu_phys_sec_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 pwr_falcon_bootvec_r(void) { - return 0x0010a104; + return 0x0010a104U; } static inline u32 pwr_falcon_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_falcon_dmactl_r(void) { - return 0x0010a10c; + return 0x0010a10cU; } static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_falcon_hwcfg_r(void) { - return 0x0010a108; + return 0x0010a108U; } static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) { - return (r >> 9) & 0x1ff; + return (r >> 9U) & 0x1ffU; } static inline u32 pwr_falcon_dmatrfbase_r(void) { - return 0x0010a110; + return 0x0010a110U; } static inline u32 pwr_falcon_dmatrfbase1_r(void) { - return 0x0010a128; + return 0x0010a128U; } static inline u32 pwr_falcon_dmatrfmoffs_r(void) { - return 0x0010a114; + return 0x0010a114U; } static inline u32 pwr_falcon_dmatrfcmd_r(void) { - return 0x0010a118; + return 0x0010a118U; } static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 pwr_falcon_dmatrffboffs_r(void) { - return 0x0010a11c; + return 0x0010a11cU; } static inline u32 pwr_falcon_exterraddr_r(void) { - return 0x0010a168; + return 0x0010a168U; } static inline u32 pwr_falcon_exterrstat_r(void) { - return 0x0010a16c; + return 0x0010a16cU; } static inline u32 pwr_falcon_exterrstat_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 pwr_falcon_exterrstat_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pwr_pmu_falcon_icd_cmd_r(void) { - return 0x0010a200; + return 0x0010a200U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 pwr_pmu_falcon_icd_rdata_r(void) { - return 0x0010a20c; + return 0x0010a20cU; } static inline u32 pwr_falcon_dmemc_r(u32 i) { - return 0x0010a1c0 + i*8; + return 0x0010a1c0U + i*8U; } static inline u32 pwr_falcon_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 pwr_falcon_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_dmemc_blk_m(void) { - return 0xff << 8; + return 0xffU << 8U; } static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_dmemd_r(u32 i) { - return 0x0010a1c4 + i*8; + return 0x0010a1c4U + i*8U; } static inline u32 pwr_pmu_new_instblk_r(void) { - return 0x0010a480; + return 0x0010a480U; } static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 pwr_pmu_new_instblk_target_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_pmu_mutex_id_r(void) { - return 0x0010a488; + return 0x0010a488U; } static inline u32 pwr_pmu_mutex_id_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_id_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 pwr_pmu_mutex_id_release_r(void) { - return 0x0010a48c; + return 0x0010a48cU; } static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_mutex_r(u32 i) { - return 0x0010a580 + i*4; + return 0x0010a580U + i*4U; } static inline u32 pwr_pmu_mutex__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 pwr_pmu_mutex_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_queue_head_r(u32 i) { - return 0x0010a800 + i*4; + return 0x0010a800U + i*4U; } static inline u32 pwr_pmu_queue_head__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_head_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_head_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_queue_tail_r(u32 i) { - return 0x0010a820 + i*4; + return 0x0010a820U + i*4U; } static inline u32 pwr_pmu_queue_tail__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_tail_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_tail_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_head_r(void) { - return 0x0010a4c8; + return 0x0010a4c8U; } static inline u32 pwr_pmu_msgq_head_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_head_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_tail_r(void) { - return 0x0010a4cc; + return 0x0010a4ccU; } static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_idle_mask_r(u32 i) { - return 0x0010a504 + i*16; + return 0x0010a504U + i*16U; } static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pwr_pmu_idle_count_r(u32 i) { - return 0x0010a508 + i*16; + return 0x0010a508U + i*16U; } static inline u32 pwr_pmu_idle_count_value_f(u32 v) { - return (v & 0x7fffffff) << 0; + return (v & 0x7fffffffU) << 0U; } static inline u32 pwr_pmu_idle_count_value_v(u32 r) { - return (r >> 0) & 0x7fffffff; + return (r >> 0U) & 0x7fffffffU; } static inline u32 pwr_pmu_idle_count_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 pwr_pmu_idle_ctrl_r(u32 i) { - return 0x0010a50c + i*16; + return 0x0010a50cU + i*16U; } static inline u32 pwr_pmu_idle_ctrl_value_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) { - return 0x3; + return 0x3U; } static inline u32 pwr_pmu_idle_ctrl_filter_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) { - return 0x0010a9f0 + i*8; + return 0x0010a9f0U + i*8U; } static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) { - return 0x0010a9f4 + i*8; + return 0x0010a9f4U + i*8U; } static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) { - return 0x0010aa30 + i*8; + return 0x0010aa30U + i*8U; } static inline u32 pwr_pmu_debug_r(u32 i) { - return 0x0010a5c0 + i*4; + return 0x0010a5c0U + i*4U; } static inline u32 pwr_pmu_debug__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pwr_pmu_mailbox_r(u32 i) { - return 0x0010a450 + i*4; + return 0x0010a450U + i*4U; } static inline u32 pwr_pmu_mailbox__size_1_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 pwr_pmu_bar0_addr_r(void) { - return 0x0010a7a0; + return 0x0010a7a0U; } static inline u32 pwr_pmu_bar0_data_r(void) { - return 0x0010a7a4; + return 0x0010a7a4U; } static inline u32 pwr_pmu_bar0_ctl_r(void) { - return 0x0010a7ac; + return 0x0010a7acU; } static inline u32 pwr_pmu_bar0_timeout_r(void) { - return 0x0010a7a8; + return 0x0010a7a8U; } static inline u32 pwr_pmu_bar0_fecs_error_r(void) { - return 0x0010a988; + return 0x0010a988U; } static inline u32 pwr_pmu_bar0_error_status_r(void) { - return 0x0010a7b0; + return 0x0010a7b0U; } static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) { - return 0x0010a6c0 + i*4; + return 0x0010a6c0U + i*4U; } static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) { - return 0x0010a6e8 + i*4; + return 0x0010a6e8U + i*4U; } static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) { - return 0x0010a710 + i*4; + return 0x0010a710U + i*4U; } static inline u32 pwr_pmu_pg_intren_r(u32 i) { - return 0x0010a760 + i*4; + return 0x0010a760U + i*4U; } static inline u32 pwr_fbif_transcfg_r(u32 i) { - return 0x0010ae00 + i*4; + return 0x0010ae00U + i*4U; } static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_fbif_transcfg_mem_type_s(void) { - return 1; + return 1U; } static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) { - return 0x4; + return 0x4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index fe8bcd6b..1191e580 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -58,619 +58,619 @@ static inline u32 ram_in_ramfc_s(void) { - return 4096; + return 4096U; } static inline u32 ram_in_ramfc_w(void) { - return 0; + return 0U; } static inline u32 ram_in_page_dir_base_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_page_dir_base_target_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 ram_in_page_dir_base_vol_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 ram_in_page_dir_base_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 ram_in_big_page_size_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 ram_in_big_page_size_w(void) { - return 128; + return 128U; } static inline u32 ram_in_big_page_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_big_page_size_64kb_f(void) { - return 0x800; + return 0x800U; } static inline u32 ram_in_page_dir_base_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_page_dir_base_lo_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_page_dir_base_hi_w(void) { - return 129; + return 129U; } static inline u32 ram_in_engine_cs_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_cs_wfi_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_cs_wfi_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_engine_cs_fg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_cs_fg_f(void) { - return 0x8; + return 0x8U; } static inline u32 ram_in_engine_wfi_mode_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_engine_wfi_mode_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_mode_physical_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_mode_virtual_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_wfi_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_engine_wfi_target_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_engine_wfi_target_local_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_engine_wfi_ptr_lo_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_in_engine_wfi_ptr_hi_w(void) { - return 133; + return 133U; } static inline u32 ram_in_engine_wfi_veid_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ram_in_engine_wfi_veid_w(void) { - return 134; + return 134U; } static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) { - return 136; + return 136U; } static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) { - return 137; + return 137U; } static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) { - return (v & 0x3) << (0 + i*0); + return (v & 0x3U) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) { - return (v & 0x1) << (2 + i*0); + return (v & 0x1U) << (2U + i*0U); } static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) { - return (v & 0x1) << (4 + i*0); + return (v & 0x1U) << (4U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) { - return (v & 0x1) << (5 + i*0); + return (v & 0x1U) << (5U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) { - return (v & 0x1) << (10 + i*0); + return (v & 0x1U) << (10U + i*0U); } static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) { - return (v & 0x1) << (11 + i*0); + return (v & 0x1U) << (11U + i*0U); } static inline u32 ram_in_sc_big_page_size__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_big_page_size_64kb_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) { - return (v & 0xfffff) << (12 + i*0); + return (v & 0xfffffU) << (12U + i*0U); } static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) { - return (v & 0xffffffff) << (0 + i*0); + return (v & 0xffffffffU) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_sc_page_dir_base_target_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_big_page_size_0_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_sc_big_page_size_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) { - return 169; + return 169U; } static inline u32 ram_in_base_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ram_in_alloc_size_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ram_fc_size_val_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_fc_gp_put_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_userd_w(void) { - return 2; + return 2U; } static inline u32 ram_fc_userd_hi_w(void) { - return 3; + return 3U; } static inline u32 ram_fc_signature_w(void) { - return 4; + return 4U; } static inline u32 ram_fc_gp_get_w(void) { - return 5; + return 5U; } static inline u32 ram_fc_pb_get_w(void) { - return 6; + return 6U; } static inline u32 ram_fc_pb_get_hi_w(void) { - return 7; + return 7U; } static inline u32 ram_fc_pb_top_level_get_w(void) { - return 8; + return 8U; } static inline u32 ram_fc_pb_top_level_get_hi_w(void) { - return 9; + return 9U; } static inline u32 ram_fc_acquire_w(void) { - return 12; + return 12U; } static inline u32 ram_fc_sem_addr_hi_w(void) { - return 14; + return 14U; } static inline u32 ram_fc_sem_addr_lo_w(void) { - return 15; + return 15U; } static inline u32 ram_fc_sem_payload_lo_w(void) { - return 16; + return 16U; } static inline u32 ram_fc_sem_payload_hi_w(void) { - return 39; + return 39U; } static inline u32 ram_fc_sem_execute_w(void) { - return 17; + return 17U; } static inline u32 ram_fc_gp_base_w(void) { - return 18; + return 18U; } static inline u32 ram_fc_gp_base_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_fc_gp_fetch_w(void) { - return 20; + return 20U; } static inline u32 ram_fc_pb_fetch_w(void) { - return 21; + return 21U; } static inline u32 ram_fc_pb_fetch_hi_w(void) { - return 22; + return 22U; } static inline u32 ram_fc_pb_put_w(void) { - return 23; + return 23U; } static inline u32 ram_fc_pb_put_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_fc_pb_header_w(void) { - return 33; + return 33U; } static inline u32 ram_fc_pb_count_w(void) { - return 34; + return 34U; } static inline u32 ram_fc_subdevice_w(void) { - return 37; + return 37U; } static inline u32 ram_fc_target_w(void) { - return 43; + return 43U; } static inline u32 ram_fc_hce_ctrl_w(void) { - return 57; + return 57U; } static inline u32 ram_fc_chid_w(void) { - return 58; + return 58U; } static inline u32 ram_fc_chid_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_fc_chid_id_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_config_w(void) { - return 61; + return 61U; } static inline u32 ram_fc_runlist_timeslice_w(void) { - return 62; + return 62U; } static inline u32 ram_fc_set_channel_info_w(void) { - return 63; + return 63U; } static inline u32 ram_userd_base_shift_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 ram_userd_chan_size_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_userd_put_w(void) { - return 16; + return 16U; } static inline u32 ram_userd_get_w(void) { - return 17; + return 17U; } static inline u32 ram_userd_ref_w(void) { - return 18; + return 18U; } static inline u32 ram_userd_put_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_userd_ref_threshold_w(void) { - return 20; + return 20U; } static inline u32 ram_userd_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_userd_get_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_userd_gp_get_w(void) { - return 34; + return 34U; } static inline u32 ram_userd_gp_put_w(void) { - return 35; + return 35U; } static inline u32 ram_userd_gp_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_gp_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_rl_entry_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ram_rl_entry_type_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 ram_rl_entry_type_channel_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_type_tsg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) { - return (v & 0x3) << 4; + return (v & 0x3U) << 4U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) { @@ -682,94 +682,94 @@ static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) } static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { - return (v & 0x3) << 6; + return (v & 0x3U) << 6U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_rl_entry_tsg_length_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_min_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_tsg_length_max_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index b47e37f4..ce265901 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -58,187 +58,187 @@ static inline u32 therm_use_a_r(void) { - return 0x00020798; + return 0x00020798U; } static inline u32 therm_use_a_ext_therm_0_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_use_a_ext_therm_1_enable_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_use_a_ext_therm_2_enable_f(void) { - return 0x4; + return 0x4U; } static inline u32 therm_evt_ext_therm_0_r(void) { - return 0x00020700; + return 0x00020700U; } static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) { - return (v & 0x3) << 30; + return (v & 0x3U) << 30U; } static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_evt_ext_therm_1_r(void) { - return 0x00020704; + return 0x00020704U; } static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) { - return (v & 0x3) << 30; + return (v & 0x3U) << 30U; } static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_evt_ext_therm_2_r(void) { - return 0x00020708; + return 0x00020708U; } static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) { - return (v & 0x3) << 30; + return (v & 0x3U) << 30U; } static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_weight_1_r(void) { - return 0x00020024; + return 0x00020024U; } static inline u32 therm_config1_r(void) { - return 0x00020050; + return 0x00020050U; } static inline u32 therm_config2_r(void) { - return 0x00020130; + return 0x00020130U; } static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 therm_config2_grad_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 therm_gate_ctrl_r(u32 i) { - return 0x00020200 + i*4; + return 0x00020200U + i*4U; } static inline u32 therm_gate_ctrl_eng_clk_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 therm_gate_ctrl_eng_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_gate_ctrl_blk_clk_m(void) { - return 0x3 << 2; + return 0x3U << 2U; } static inline u32 therm_gate_ctrl_blk_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) { - return 0x4; + return 0x4U; } static inline u32 therm_gate_ctrl_idle_holdoff_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) { - return 0x10; + return 0x10U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { - return 0x1f << 8; + return 0x1fU << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) { @@ -246,11 +246,11 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { - return (v & 0x7) << 13; + return (v & 0x7U) << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { - return 0x7 << 13; + return 0x7U << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) { @@ -258,11 +258,11 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) } static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { - return 0xf << 16; + return 0xfU << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) { @@ -270,11 +270,11 @@ static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) } static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { - return 0xf << 20; + return 0xfU << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) { @@ -282,11 +282,11 @@ static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) } static inline u32 therm_fecs_idle_filter_r(void) { - return 0x00020288; + return 0x00020288U; } static inline u32 therm_fecs_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_fecs_idle_filter_value__prod_f(void) { @@ -294,11 +294,11 @@ static inline u32 therm_fecs_idle_filter_value__prod_f(void) } static inline u32 therm_hubmmu_idle_filter_r(void) { - return 0x0002028c; + return 0x0002028cU; } static inline u32 therm_hubmmu_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) { @@ -306,130 +306,130 @@ static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) } static inline u32 therm_clk_slowdown_r(u32 i) { - return 0x00020160 + i*4; + return 0x00020160U + i*4U; } static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) { - return (v & 0x3f) << 16; + return (v & 0x3fU) << 16U; } static inline u32 therm_clk_slowdown_idle_factor_m(void) { - return 0x3f << 16; + return 0x3fU << 16U; } static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) { - return (r >> 16) & 0x3f; + return (r >> 16U) & 0x3fU; } static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_grad_stepping_table_r(u32 i) { - return 0x000202c8 + i*4; + return 0x000202c8U + i*4U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) { - return 0x6; + return 0x6U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) { - return 0xe; + return 0xeU; } static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) { - return (v & 0x3f) << 12; + return (v & 0x3fU) << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) { - return 0x3f << 12; + return 0x3fU << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) { - return (v & 0x3f) << 18; + return (v & 0x3fU) << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) { - return 0x3f << 18; + return 0x3fU << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) { - return 0x3f << 24; + return 0x3fU << 24U; } static inline u32 therm_grad_stepping0_r(void) { - return 0x000202c0; + return 0x000202c0U; } static inline u32 therm_grad_stepping0_feature_s(void) { - return 1; + return 1U; } static inline u32 therm_grad_stepping0_feature_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 therm_grad_stepping0_feature_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 therm_grad_stepping0_feature_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 therm_grad_stepping0_feature_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping1_r(void) { - return 0x000202c4; + return 0x000202c4U; } static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 therm_clk_timing_r(u32 i) { - return 0x000203c0 + i*4; + return 0x000203c0U + i*4U; } static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 therm_clk_timing_grad_slowdown_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h index 1181f177..61440213 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -58,58 +58,58 @@ static inline u32 timer_pri_timeout_r(void) { - return 0x00009080; + return 0x00009080U; } static inline u32 timer_pri_timeout_period_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 timer_pri_timeout_period_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 timer_pri_timeout_period_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 timer_pri_timeout_en_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 timer_pri_timeout_en_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 timer_pri_timeout_en_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 timer_pri_timeout_en_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 timer_pri_timeout_en_en_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 timer_pri_timeout_save_0_r(void) { - return 0x00009084; + return 0x00009084U; } static inline u32 timer_pri_timeout_save_1_r(void) { - return 0x00009088; + return 0x00009088U; } static inline u32 timer_pri_timeout_fecs_errcode_r(void) { - return 0x0000908c; + return 0x0000908cU; } static inline u32 timer_time_0_r(void) { - return 0x00009400; + return 0x00009400U; } static inline u32 timer_time_1_r(void) { - return 0x00009410; + return 0x00009410U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 694257ed..89e4aebb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -58,178 +58,178 @@ static inline u32 top_num_gpcs_r(void) { - return 0x00022430; + return 0x00022430U; } static inline u32 top_num_gpcs_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_tpc_per_gpc_r(void) { - return 0x00022434; + return 0x00022434U; } static inline u32 top_tpc_per_gpc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_fbps_r(void) { - return 0x00022438; + return 0x00022438U; } static inline u32 top_num_fbps_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_ltc_per_fbp_r(void) { - return 0x00022450; + return 0x00022450U; } static inline u32 top_ltc_per_fbp_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_slices_per_ltc_r(void) { - return 0x0002245c; + return 0x0002245cU; } static inline u32 top_slices_per_ltc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_ltcs_r(void) { - return 0x00022454; + return 0x00022454U; } static inline u32 top_num_ces_r(void) { - return 0x00022444; + return 0x00022444U; } static inline u32 top_num_ces_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_device_info_r(u32 i) { - return 0x00022700 + i*4; + return 0x00022700U + i*4U; } static inline u32 top_device_info__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 top_device_info_chain_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 top_device_info_chain_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_engine_enum_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_runlist_enum_v(u32 r) { - return (r >> 21) & 0xf; + return (r >> 21U) & 0xfU; } static inline u32 top_device_info_intr_enum_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 top_device_info_reset_enum_v(u32 r) { - return (r >> 9) & 0x1f; + return (r >> 9U) & 0x1fU; } static inline u32 top_device_info_type_enum_v(u32 r) { - return (r >> 2) & 0x1fffffff; + return (r >> 2U) & 0x1fffffffU; } static inline u32 top_device_info_type_enum_graphics_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_type_enum_graphics_f(void) { - return 0x0; + return 0x0U; } static inline u32 top_device_info_type_enum_copy2_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 top_device_info_type_enum_copy2_f(void) { - return 0xc; + return 0xcU; } static inline u32 top_device_info_type_enum_lce_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 top_device_info_type_enum_lce_f(void) { - return 0x4c; + return 0x4cU; } static inline u32 top_device_info_engine_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 top_device_info_runlist_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 top_device_info_intr_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 top_device_info_reset_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_entry_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 top_device_info_entry_not_valid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_entry_enum_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 top_device_info_entry_data_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_data_type_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 top_device_info_data_type_enum2_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_data_inst_id_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_data_pri_base_v(u32 r) { - return (r >> 12) & 0xfff; + return (r >> 12U) & 0xfffU; } static inline u32 top_device_info_data_pri_base_align_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 top_device_info_data_fault_id_enum_v(u32 r) { - return (r >> 3) & 0x7f; + return (r >> 3U) & 0x7fU; } static inline u32 top_device_info_data_fault_id_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_data_fault_id_valid_v(void) { - return 0x00000001; + return 0x00000001U; } #endif -- cgit v1.2.2 From ade9f5e03f1d0fd4987fc3f9fafb12e4118ac570 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 10 Oct 2017 13:18:02 -0700 Subject: gpu: nvgpu: Remove phys_addr_t from common code Remove phys_addr_t change for corresponding change in the nvgpu main repo. JIRA NVGPU-30 JIRA NVGPU-226 Change-Id: I05a19bc51e949279edef6e9ad7161226cbca51a7 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1576466 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h index fcf99778..4b499882 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h @@ -24,12 +24,13 @@ #define __NVGPU_NVHOST_T19X_H__ #ifdef CONFIG_TEGRA_GK20A_NVHOST +#include + struct nvgpu_nvhost_dev; int nvgpu_nvhost_syncpt_unit_interface_get_aperture( struct nvgpu_nvhost_dev *nvhost_dev, - phys_addr_t *base, - size_t *size); + u64 *base, size_t *size); u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); #endif -- cgit v1.2.2 From 82f235b5299c65446398d63fd3c982853fc1de23 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 29 Sep 2017 12:41:48 -0700 Subject: gpu: nvgpu: gv100: Qualify unsigned HW constants Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: If3c1e25dcb07ce6857a4798f2c5308e2948fe5e0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1571163 Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit --- .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 84 +- .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 64 +- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 24 +- .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 198 +- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 708 +++---- .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 246 +-- .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 64 +- .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 42 +- .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 614 +++---- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 1926 ++++++++++---------- .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 280 +-- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 96 +- .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 296 +-- .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 76 +- .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 2 +- .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 54 +- .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 10 +- .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 16 +- .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 54 +- .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 438 ++--- .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 354 ++-- .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 120 +- .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 28 +- .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 88 +- .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 18 +- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 42 +- .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 74 +- 27 files changed, 3008 insertions(+), 3008 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index 2c89ccd6..7771f1ea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -58,170 +58,170 @@ static inline u32 bus_sw_scratch_r(u32 i) { - return 0x00001580 + i*4; + return 0x00001580U + i*4U; } static inline u32 bus_bar0_window_r(void) { - return 0x00001700; + return 0x00001700U; } static inline u32 bus_bar0_window_base_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 bus_bar0_window_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 bus_bar1_block_r(void) { - return 0x00001704; + return 0x00001704U; } static inline u32 bus_bar1_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar1_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar1_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar2_block_r(void) { - return 0x00001714; + return 0x00001714U; } static inline u32 bus_bar2_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar2_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar2_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar1_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bar2_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bind_status_r(void) { - return 0x00001710; + return 0x00001710U; } static inline u32 bus_bind_status_bar1_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 bus_bind_status_bar1_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_outstanding_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 bus_bind_status_bar2_pending_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 bus_bind_status_bar2_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_pending_busy_f(void) { - return 0x4; + return 0x4U; } static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 bus_bind_status_bar2_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_outstanding_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 bus_intr_0_r(void) { - return 0x00001100; + return 0x00001100U; } static inline u32 bus_intr_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 bus_intr_en_0_r(void) { - return 0x00001140; + return 0x00001140U; } static inline u32 bus_intr_en_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_en_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_en_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index ae0179f2..b1478037 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -58,130 +58,130 @@ static inline u32 ccsr_channel_inst_r(u32 i) { - return 0x00800000 + i*8; + return 0x00800000U + i*8U; } static inline u32 ccsr_channel_inst__size_1_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ccsr_channel_inst_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 ccsr_channel_inst_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 ccsr_channel_inst_bind_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_bind_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 ccsr_channel_r(u32 i) { - return 0x00800004 + i*8; + return 0x00800004U + i*8U; } static inline u32 ccsr_channel__size_1_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ccsr_channel_enable_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ccsr_channel_enable_set_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ccsr_channel_enable_set_true_f(void) { - return 0x400; + return 0x400U; } static inline u32 ccsr_channel_enable_clr_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 ccsr_channel_status_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 ccsr_channel_next_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 ccsr_channel_next_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_force_ctx_reload_true_f(void) { - return 0x100; + return 0x100U; } static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 ccsr_channel_eng_faulted_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 ccsr_channel_eng_faulted_v(u32 r) { - return (r >> 23) & 0x1; + return (r >> 23U) & 0x1U; } static inline u32 ccsr_channel_eng_faulted_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 ccsr_channel_eng_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_busy_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h index 6923d921..18b5fc66 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -58,50 +58,50 @@ static inline u32 ce_intr_status_r(u32 i) { - return 0x00104410 + i*128; + return 0x00104410U + i*128U; } static inline u32 ce_intr_status_blockpipe_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_blockpipe_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_nonblockpipe_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_nonblockpipe_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_launcherr_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_launcherr_reset_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_invalid_config_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_invalid_config_reset_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_pce_map_r(void) { - return 0x00104028; + return 0x00104028U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h index 86075656..cd792835 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -58,398 +58,398 @@ static inline u32 ctxsw_prog_fecs_header_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 ctxsw_prog_main_image_patch_count_o(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_context_id_o(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 ctxsw_prog_main_image_zcull_o(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_pm_o(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) { - return 0x8; + return 0x8U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) { - return 0x00000060; + return 0x00000060U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) { - return 0x00000094; + return 0x00000094U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) { - return 0x600dc0de; + return 0x600dc0deU; } static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_local_image_ppc_info_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_local_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) { - return 0xad0becab; + return 0xad0becabU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) { - return 2; + return 2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) { - return 0x2; + return 0x2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 ctxsw_prog_main_image_misc_options_o(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) { - return 0x2; + return 0x2U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index 33c08bad..3bba3fb8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -58,1418 +58,1418 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) { - return 0x00100800; + return 0x00100800U; } static inline u32 fb_mmu_ctrl_r(void) { - return 0x00100c80; + return 0x00100c80U; } static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) { - return (r >> 11) & 0x1; + return (r >> 11U) & 0x1U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_priv_mmu_phy_secure_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 fb_mmu_invalidate_pdb_r(void) { - return 0x00100cb8; + return 0x00100cb8U; } static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_invalidate_r(void) { - return 0x00100cbc; + return 0x00100cbcU; } static inline u32 fb_mmu_invalidate_all_va_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_invalidate_replay_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_replay_f(u32 v) { - return (v & 0x7) << 3; + return (v & 0x7U) << 3U; } static inline u32 fb_mmu_invalidate_replay_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 fb_mmu_invalidate_replay_v(u32 r) { - return (r >> 3) & 0x7; + return (r >> 3U) & 0x7U; } static inline u32 fb_mmu_invalidate_replay_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_replay_start_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_invalidate_sys_membar_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_invalidate_ack_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_invalidate_ack_f(u32 v) { - return (v & 0x3) << 7; + return (v & 0x3U) << 7U; } static inline u32 fb_mmu_invalidate_ack_m(void) { - return 0x3 << 7; + return 0x3U << 7U; } static inline u32 fb_mmu_invalidate_ack_v(u32 r) { - return (r >> 7) & 0x3; + return (r >> 7U) & 0x3U; } static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) { - return 6; + return 6U; } static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) { - return (v & 0x3f) << 9; + return (v & 0x3fU) << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) { - return 0x3f << 9; + return 0x3fU << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) { - return (r >> 9) & 0x3f; + return (r >> 9U) & 0x3fU; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) { - return 5; + return 5U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) { - return 0x1f << 15; + return 0x1fU << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) { - return 0x7 << 24; + return 0x7U << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) { - return (r >> 24) & 0x7; + return (r >> 24U) & 0x7U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) { - return 0x5000000; + return 0x5000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) { - return 0x6000000; + return 0x6000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) { - return 0x7000000; + return 0x7000000U; } static inline u32 fb_mmu_invalidate_trigger_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_trigger_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_invalidate_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_invalidate_trigger_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_invalidate_trigger_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_debug_wr_r(void) { - return 0x00100cc8; + return 0x00100cc8U; } static inline u32 fb_mmu_debug_wr_aperture_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_debug_wr_aperture_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_wr_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_wr_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_rd_r(void) { - return 0x00100ccc; + return 0x00100cccU; } static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_rd_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_ctrl_r(void) { - return 0x00100cc4; + return 0x00100cc4U; } static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 fb_mmu_debug_ctrl_debug_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_r(void) { - return 0x00100cd0; + return 0x00100cd0U; } static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_vpr_info_fetch_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_niso_flush_sysmem_addr_r(void) { - return 0x00100c10; + return 0x00100c10U; } static inline u32 fb_niso_intr_r(void) { - return 0x00100a20; + return 0x00100a20U; } static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_r(u32 i) { - return 0x00100a24 + i*4; + return 0x00100a24U + i*4U; } static inline u32 fb_niso_intr_en__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_set_r(u32 i) { - return 0x00100a2c + i*4; + return 0x00100a2cU + i*4U; } static inline u32 fb_niso_intr_en_set__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_clr_r(u32 i) { - return 0x00100a34 + i*4; + return 0x00100a34U + i*4U; } static inline u32 fb_niso_intr_en_clr__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) { - return 0x00100e24 + i*20; + return 0x00100e24U + i*20U; } static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 1; + return (v & 0x3U) << 1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) { - return (r >> 1) & 0x3; + return (r >> 1U) & 0x3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) { - return 0x00100e28 + i*20; + return 0x00100e28U + i*20U; } static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_buffer_get_r(u32 i) { - return 0x00100e2c + i*20; + return 0x00100e2cU + i*20U; } static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_put_r(u32 i) { - return 0x00100e30 + i*20; + return 0x00100e30U + i*20U; } static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_size_r(u32 i) { - return 0x00100e34 + i*20; + return 0x00100e34U + i*20U; } static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_addr_lo_r(void) { - return 0x00100e4c; + return 0x00100e4cU; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_addr_hi_r(void) { - return 0x00100e50; + return 0x00100e50U; } static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_inst_lo_r(void) { - return 0x00100e54; + return 0x00100e54U; } static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) { - return (r >> 10) & 0x3; + return (r >> 10U) & 0x3U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_inst_hi_r(void) { - return 0x00100e58; + return 0x00100e58U; } static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_info_r(void) { - return 0x00100e5c; + return 0x00100e5cU; } static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 fb_mmu_fault_info_client_v(u32 r) { - return (r >> 8) & 0x7f; + return (r >> 8U) & 0x7fU; } static inline u32 fb_mmu_fault_info_access_type_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 fb_mmu_fault_info_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_info_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_status_r(void) { - return 0x00100e60; + return 0x00100e60U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_replayable_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_set_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_fault_status_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) { - return 0x200; + return 0x200U; } static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) { - return 0x400; + return 0x400U; } static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fb_mmu_fault_status_busy_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_busy_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_status_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_status_valid_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_local_memory_range_r(void) { - return 0x00100ce0; + return 0x00100ce0U; } static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) { - return (r >> 4) & 0x3f; + return (r >> 4U) & 0x3fU; } static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_niso_scrub_status_r(void) { - return 0x00100b20; + return 0x00100b20U; } static inline u32 fb_niso_scrub_status_flag_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fb_mmu_priv_level_mask_r(void) { - return 0x00100cdc; + return 0x00100cdcU; } static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h index 1578a124..743afb1e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -58,494 +58,494 @@ static inline u32 fifo_bar1_base_r(void) { - return 0x00002254; + return 0x00002254U; } static inline u32 fifo_bar1_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_bar1_base_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fifo_bar1_base_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_bar1_base_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_userd_writeback_r(void) { - return 0x0000225c; + return 0x0000225cU; } static inline u32 fifo_userd_writeback_timer_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_userd_writeback_timer_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_userd_writeback_timer_shorter_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_userd_writeback_timer_100us_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 fifo_userd_writeback_timescale_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 fifo_userd_writeback_timescale_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_runlist_base_r(void) { - return 0x00002270; + return 0x00002270U; } static inline u32 fifo_runlist_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_runlist_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 fifo_runlist_r(void) { - return 0x00002274; + return 0x00002274U; } static inline u32 fifo_runlist_engine_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 fifo_eng_runlist_base_r(u32 i) { - return 0x00002280 + i*8; + return 0x00002280U + i*8U; } static inline u32 fifo_eng_runlist_base__size_1_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 fifo_eng_runlist_r(u32 i) { - return 0x00002284 + i*8; + return 0x00002284U + i*8U; } static inline u32 fifo_eng_runlist__size_1_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 fifo_eng_runlist_length_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fifo_eng_runlist_length_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 fifo_eng_runlist_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_pb_timeslice_r(u32 i) { - return 0x00002350 + i*4; + return 0x00002350U + i*4U; } static inline u32 fifo_pb_timeslice_timeout_16_f(void) { - return 0x10; + return 0x10U; } static inline u32 fifo_pb_timeslice_timescale_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_pb_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_pbdma_map_r(u32 i) { - return 0x00002390 + i*4; + return 0x00002390U + i*4U; } static inline u32 fifo_intr_0_r(void) { - return 0x00002100; + return 0x00002100U; } static inline u32 fifo_intr_0_bind_error_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_bind_error_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_sched_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_sched_error_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_chsw_error_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_chsw_error_reset_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_lb_error_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_lb_error_reset_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_intr_0_runlist_event_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fifo_intr_0_channel_intr_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_intr_en_0_r(void) { - return 0x00002140; + return 0x00002140U; } static inline u32 fifo_intr_en_0_sched_error_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 fifo_intr_en_0_sched_error_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fifo_intr_en_1_r(void) { - return 0x00002528; + return 0x00002528U; } static inline u32 fifo_intr_bind_error_r(void) { - return 0x0000252c; + return 0x0000252cU; } static inline u32 fifo_intr_sched_error_r(void) { - return 0x0000254c; + return 0x0000254cU; } static inline u32 fifo_intr_sched_error_code_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_intr_chsw_error_r(void) { - return 0x0000256c; + return 0x0000256cU; } static inline u32 fifo_intr_pbdma_id_r(void) { - return 0x000025a0; + return 0x000025a0U; } static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 fifo_intr_runlist_r(void) { - return 0x00002a00; + return 0x00002a00U; } static inline u32 fifo_fb_timeout_r(void) { - return 0x00002a04; + return 0x00002a04U; } static inline u32 fifo_fb_timeout_period_m(void) { - return 0x3fffffff << 0; + return 0x3fffffffU << 0U; } static inline u32 fifo_fb_timeout_period_max_f(void) { - return 0x3fffffff; + return 0x3fffffffU; } static inline u32 fifo_fb_timeout_period_init_f(void) { - return 0x3c00; + return 0x3c00U; } static inline u32 fifo_sched_disable_r(void) { - return 0x00002630; + return 0x00002630U; } static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_sched_disable_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_sched_disable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_runlist_preempt_r(void) { - return 0x00002638; + return 0x00002638U; } static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_preempt_r(void) { - return 0x00002634; + return 0x00002634U; } static inline u32 fifo_preempt_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_preempt_type_channel_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_preempt_type_tsg_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_preempt_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_preempt_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_engine_status_r(u32 i) { - return 0x00002640 + i*8; + return 0x00002640U + i*8U; } static inline u32 fifo_engine_status__size_1_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 fifo_engine_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_engine_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_engine_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_engine_status_ctx_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_engine_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_engine_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_engine_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_eng_reload_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fifo_engine_status_faulted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fifo_engine_status_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_engine_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fifo_engine_status_engine_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_engine_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fifo_pbdma_status_r(u32 i) { - return 0x00003080 + i*4; + return 0x00003080U + i*4U; } static inline u32 fifo_pbdma_status__size_1_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 fifo_pbdma_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_pbdma_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_pbdma_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_pbdma_status_chan_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_pbdma_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_chsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_cfg0_r(void) { - return 0x00002004; + return 0x00002004U; } static inline u32 fifo_cfg0_num_pbdma_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fifo_fb_iface_r(void) { - return 0x000026f0; + return 0x000026f0U; } static inline u32 fifo_fb_iface_control_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fifo_fb_iface_control_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_fb_iface_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 fifo_fb_iface_status_enabled_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h index 549c2f8f..b6045626 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -58,130 +58,130 @@ static inline u32 flush_l2_system_invalidate_r(void) { - return 0x00070004; + return 0x00070004U; } static inline u32 flush_l2_system_invalidate_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_system_invalidate_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_system_invalidate_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_r(void) { - return 0x00070010; + return 0x00070010U; } static inline u32 flush_l2_flush_dirty_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_flush_dirty_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_r(void) { - return 0x0007000c; + return 0x0007000cU; } static inline u32 flush_l2_clean_comptags_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_clean_comptags_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_r(void) { - return 0x00070000; + return 0x00070000U; } static inline u32 flush_fb_flush_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_fb_flush_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_fb_flush_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_fb_flush_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h index 0c2334da..f7eacd29 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -58,86 +58,86 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) { - return 0x00021c38 + i*4; + return 0x00021c38U + i*4U; } static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) { - return 0x00021838 + i*4; + return 0x00021838U + i*4U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) { - return 0x00021944; + return 0x00021944U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) { - return 0x00021948; + return 0x00021948U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) { - return 0x1; + return 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fuse_status_opt_fbio_r(void) { - return 0x00021c14; + return 0x00021c14U; } static inline u32 fuse_status_opt_fbio_data_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fuse_status_opt_fbio_data_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fuse_status_opt_fbio_data_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) { - return 0x00021d70 + i*4; + return 0x00021d70U + i*4U; } static inline u32 fuse_status_opt_fbp_r(void) { - return 0x00021d38; + return 0x00021d38U; } static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fuse_opt_ecc_en_r(void) { - return 0x00021228; + return 0x00021228U; } static inline u32 fuse_opt_feature_fuses_override_disable_r(void) { - return 0x000213f0; + return 0x000213f0U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h index 0aa2743d..cf89f5f8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -58,1230 +58,1230 @@ static inline u32 gmmu_new_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_aperture_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pde_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pde_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_pde__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_vol_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_vol_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde__size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gmmu_new_pte__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_pte_valid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_valid_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gmmu_new_pte_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_privilege_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_privilege_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 gmmu_new_pte_privilege_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_address_vid_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_vid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pte_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pte_read_only_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_read_only_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 gmmu_new_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 4; + return (v & 0x3ffffU) << 4U; } static inline u32 gmmu_new_pte_comptagline_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_kind_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gmmu_new_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_pte_kind_f(u32 v) { - return (v & 0xff) << 4; + return (v & 0xffU) << 4U; } static inline u32 gmmu_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_pte_kind_invalid_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 gmmu_pte_kind_pitch_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_pte_kind_z16_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_pte_kind_z16_2c_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 gmmu_pte_kind_z16_2z_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 gmmu_pte_kind_z16_2cz_v(void) { - return 0x00000036; + return 0x00000036U; } static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) { - return 0x00000037; + return 0x00000037U; } static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) { - return 0x0000005f; + return 0x0000005fU; } static inline u32 gmmu_pte_kind_s8z24_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 gmmu_pte_kind_s8z24_1z_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) { - return 0x00000017; + return 0x00000017U; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) { - return 0x00000019; + return 0x00000019U; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) { - return 0x0000001b; + return 0x0000001bU; } static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) { - return 0x0000001d; + return 0x0000001dU; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) { - return 0x0000001e; + return 0x0000001eU; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) { - return 0x00000022; + return 0x00000022U; } static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) { - return 0x00000023; + return 0x00000023U; } static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) { - return 0x00000024; + return 0x00000024U; } static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) { - return 0x00000026; + return 0x00000026U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) { - return 0x00000027; + return 0x00000027U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) { - return 0x00000029; + return 0x00000029U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) { - return 0x0000002e; + return 0x0000002eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) { - return 0x0000002f; + return 0x0000002fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) { - return 0x00000033; + return 0x00000033U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) { - return 0x00000034; + return 0x00000034U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) { - return 0x00000035; + return 0x00000035U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) { - return 0x0000003b; + return 0x0000003bU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) { - return 0x0000003d; + return 0x0000003dU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) { - return 0x0000003e; + return 0x0000003eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) { - return 0x0000003f; + return 0x0000003fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) { - return 0x00000041; + return 0x00000041U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) { - return 0x00000042; + return 0x00000042U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) { - return 0x00000043; + return 0x00000043U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) { - return 0x00000044; + return 0x00000044U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) { - return 0x00000045; + return 0x00000045U; } static inline u32 gmmu_pte_kind_z24s8_v(void) { - return 0x00000046; + return 0x00000046U; } static inline u32 gmmu_pte_kind_z24s8_1z_v(void) { - return 0x00000047; + return 0x00000047U; } static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) { - return 0x00000048; + return 0x00000048U; } static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) { - return 0x00000049; + return 0x00000049U; } static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) { - return 0x0000004a; + return 0x0000004aU; } static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) { - return 0x0000004b; + return 0x0000004bU; } static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) { - return 0x0000004c; + return 0x0000004cU; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) { - return 0x0000004d; + return 0x0000004dU; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) { - return 0x0000004e; + return 0x0000004eU; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) { - return 0x0000004f; + return 0x0000004fU; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) { - return 0x00000051; + return 0x00000051U; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) { - return 0x00000052; + return 0x00000052U; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) { - return 0x00000053; + return 0x00000053U; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) { - return 0x00000054; + return 0x00000054U; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) { - return 0x00000055; + return 0x00000055U; } static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) { - return 0x00000056; + return 0x00000056U; } static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) { - return 0x00000057; + return 0x00000057U; } static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) { - return 0x00000058; + return 0x00000058U; } static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) { - return 0x00000059; + return 0x00000059U; } static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) { - return 0x0000005a; + return 0x0000005aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) { - return 0x0000005b; + return 0x0000005bU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) { - return 0x0000005c; + return 0x0000005cU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) { - return 0x0000005d; + return 0x0000005dU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) { - return 0x0000005e; + return 0x0000005eU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) { - return 0x00000063; + return 0x00000063U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) { - return 0x00000065; + return 0x00000065U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) { - return 0x00000066; + return 0x00000066U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) { - return 0x00000067; + return 0x00000067U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) { - return 0x00000069; + return 0x00000069U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) { - return 0x0000006a; + return 0x0000006aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) { - return 0x0000006f; + return 0x0000006fU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) { - return 0x00000071; + return 0x00000071U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) { - return 0x00000072; + return 0x00000072U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) { - return 0x00000073; + return 0x00000073U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) { - return 0x00000075; + return 0x00000075U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) { - return 0x00000076; + return 0x00000076U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) { - return 0x00000077; + return 0x00000077U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) { - return 0x00000079; + return 0x00000079U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) { - return 0x0000007a; + return 0x0000007aU; } static inline u32 gmmu_pte_kind_zf32_v(void) { - return 0x0000007b; + return 0x0000007bU; } static inline u32 gmmu_pte_kind_zf32_1z_v(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) { - return 0x0000007d; + return 0x0000007dU; } static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) { - return 0x0000007e; + return 0x0000007eU; } static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) { - return 0x0000007f; + return 0x0000007fU; } static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gmmu_pte_kind_zf32_2cs_v(void) { - return 0x00000081; + return 0x00000081U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) { - return 0x00000082; + return 0x00000082U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) { - return 0x00000083; + return 0x00000083U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) { - return 0x00000085; + return 0x00000085U; } static inline u32 gmmu_pte_kind_zf32_2cz_v(void) { - return 0x00000086; + return 0x00000086U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) { - return 0x00000087; + return 0x00000087U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) { - return 0x00000088; + return 0x00000088U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) { - return 0x00000089; + return 0x00000089U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) { - return 0x0000008a; + return 0x0000008aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) { - return 0x0000008b; + return 0x0000008bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) { - return 0x0000008c; + return 0x0000008cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) { - return 0x0000008d; + return 0x0000008dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) { - return 0x0000008e; + return 0x0000008eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x0000008f; + return 0x0000008fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x00000090; + return 0x00000090U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x00000091; + return 0x00000091U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x00000092; + return 0x00000092U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x00000097; + return 0x00000097U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x00000098; + return 0x00000098U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x00000099; + return 0x00000099U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x0000009a; + return 0x0000009aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x0000009b; + return 0x0000009bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x0000009c; + return 0x0000009cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x0000009d; + return 0x0000009dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x0000009e; + return 0x0000009eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x0000009f; + return 0x0000009fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000a1; + return 0x000000a1U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000a2; + return 0x000000a2U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000a3; + return 0x000000a3U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000a5; + return 0x000000a5U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000a6; + return 0x000000a6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) { - return 0x000000a7; + return 0x000000a7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) { - return 0x000000a9; + return 0x000000a9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) { - return 0x000000aa; + return 0x000000aaU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x000000ab; + return 0x000000abU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x000000ac; + return 0x000000acU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x000000ad; + return 0x000000adU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x000000ae; + return 0x000000aeU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x000000b3; + return 0x000000b3U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x000000b4; + return 0x000000b4U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x000000b5; + return 0x000000b5U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x000000b6; + return 0x000000b6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x000000b7; + return 0x000000b7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x000000b9; + return 0x000000b9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x000000ba; + return 0x000000baU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x000000bb; + return 0x000000bbU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000bd; + return 0x000000bdU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000be; + return 0x000000beU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000bf; + return 0x000000bfU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000c1; + return 0x000000c1U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000c2; + return 0x000000c2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) { - return 0x000000c3; + return 0x000000c3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) { - return 0x000000c5; + return 0x000000c5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) { - return 0x000000c6; + return 0x000000c6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) { - return 0x000000c7; + return 0x000000c7U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) { - return 0x000000ce; + return 0x000000ceU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) { - return 0x000000cf; + return 0x000000cfU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) { - return 0x000000d1; + return 0x000000d1U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) { - return 0x000000d2; + return 0x000000d2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) { - return 0x000000d3; + return 0x000000d3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) { - return 0x000000d5; + return 0x000000d5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) { - return 0x000000d6; + return 0x000000d6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) { - return 0x000000d7; + return 0x000000d7U; } static inline u32 gmmu_pte_kind_generic_16bx2_v(void) { - return 0x000000fe; + return 0x000000feU; } static inline u32 gmmu_pte_kind_c32_2c_v(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 gmmu_pte_kind_c32_2cbr_v(void) { - return 0x000000d9; + return 0x000000d9U; } static inline u32 gmmu_pte_kind_c32_2cba_v(void) { - return 0x000000da; + return 0x000000daU; } static inline u32 gmmu_pte_kind_c32_2cra_v(void) { - return 0x000000db; + return 0x000000dbU; } static inline u32 gmmu_pte_kind_c32_2bra_v(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) { - return 0x000000dd; + return 0x000000ddU; } static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) { - return 0x000000de; + return 0x000000deU; } static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) { - return 0x000000df; + return 0x000000dfU; } static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) { - return 0x000000e1; + return 0x000000e1U; } static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) { - return 0x000000e2; + return 0x000000e2U; } static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) { - return 0x000000e3; + return 0x000000e3U; } static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) { - return 0x000000e5; + return 0x000000e5U; } static inline u32 gmmu_pte_kind_c64_2c_v(void) { - return 0x000000e6; + return 0x000000e6U; } static inline u32 gmmu_pte_kind_c64_2cbr_v(void) { - return 0x000000e7; + return 0x000000e7U; } static inline u32 gmmu_pte_kind_c64_2cba_v(void) { - return 0x000000e8; + return 0x000000e8U; } static inline u32 gmmu_pte_kind_c64_2cra_v(void) { - return 0x000000e9; + return 0x000000e9U; } static inline u32 gmmu_pte_kind_c64_2bra_v(void) { - return 0x000000ea; + return 0x000000eaU; } static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) { - return 0x000000eb; + return 0x000000ebU; } static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) { - return 0x000000cd; + return 0x000000cdU; } static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) { - return 0x000000ed; + return 0x000000edU; } static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) { - return 0x000000ee; + return 0x000000eeU; } static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) { - return 0x000000ef; + return 0x000000efU; } static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) { - return 0x000000f1; + return 0x000000f1U; } static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) { - return 0x0000002d; + return 0x0000002dU; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) { - return 0x000000f2; + return 0x000000f2U; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) { - return 0x000000f3; + return 0x000000f3U; } static inline u32 gmmu_pte_kind_c128_2c_v(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 gmmu_pte_kind_c128_2cr_v(void) { - return 0x000000f5; + return 0x000000f5U; } static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) { - return 0x000000f6; + return 0x000000f6U; } static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) { - return 0x000000f7; + return 0x000000f7U; } static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) { - return 0x000000f9; + return 0x000000f9U; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) { - return 0x000000fa; + return 0x000000faU; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) { - return 0x000000fb; + return 0x000000fbU; } static inline u32 gmmu_pte_kind_x8c24_v(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) { - return 0x000000fd; + return 0x000000fdU; } static inline u32 gmmu_pte_kind_smsked_message_v(void) { - return 0x000000ca; + return 0x000000caU; } static inline u32 gmmu_pte_kind_smhost_message_v(void) { - return 0x000000cb; + return 0x000000cbU; } static inline u32 gmmu_pte_kind_s8_v(void) { - return 0x0000002a; + return 0x0000002aU; } static inline u32 gmmu_pte_kind_s8_2s_v(void) { - return 0x0000002b; + return 0x0000002bU; } static inline u32 gmmu_fault_client_type_gpc_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_fault_client_type_hub_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_type_unbound_inst_block_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) { - return 0x0000000f; + return 0x0000000fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index 750070ad..bdd749d0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -58,3854 +58,3854 @@ static inline u32 gr_intr_r(void) { - return 0x00400100; + return 0x00400100U; } static inline u32 gr_intr_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_notify_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_semaphore_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_semaphore_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_illegal_method_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_method_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_notify_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_illegal_notify_reset_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_firmware_method_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_intr_firmware_method_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_firmware_method_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_illegal_class_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_illegal_class_reset_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_fecs_error_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_fecs_error_reset_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_class_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_class_error_reset_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_exception_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_intr_exception_reset_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_fecs_intr_r(void) { - return 0x00400144; + return 0x00400144U; } static inline u32 gr_class_error_r(void) { - return 0x00400110; + return 0x00400110U; } static inline u32 gr_class_error_code_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_intr_nonstall_r(void) { - return 0x00400120; + return 0x00400120U; } static inline u32 gr_intr_nonstall_trap_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_en_r(void) { - return 0x0040013c; + return 0x0040013cU; } static inline u32 gr_exception_r(void) { - return 0x00400108; + return 0x00400108U; } static inline u32 gr_exception_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_sked_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_exception1_r(void) { - return 0x00400118; + return 0x00400118U; } static inline u32 gr_exception1_gpc_0_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception2_r(void) { - return 0x0040011c; + return 0x0040011cU; } static inline u32 gr_exception_en_r(void) { - return 0x00400138; + return 0x00400138U; } static inline u32 gr_exception_en_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_en_fe_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception_en_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_en_gpc_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 gr_exception_en_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_en_memfmt_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_exception_en_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_en_ds_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_exception1_en_r(void) { - return 0x00400130; + return 0x00400130U; } static inline u32 gr_exception2_en_r(void) { - return 0x00400134; + return 0x00400134U; } static inline u32 gr_gpfifo_ctl_r(void) { - return 0x00400500; + return 0x00400500U; } static inline u32 gr_gpfifo_ctl_access_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpfifo_ctl_access_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpfifo_ctl_access_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpfifo_status_r(void) { - return 0x00400504; + return 0x00400504U; } static inline u32 gr_trapped_addr_r(void) { - return 0x00400704; + return 0x00400704U; } static inline u32 gr_trapped_addr_mthd_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 gr_trapped_addr_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 gr_trapped_data_lo_r(void) { - return 0x00400708; + return 0x00400708U; } static inline u32 gr_trapped_data_hi_r(void) { - return 0x0040070c; + return 0x0040070cU; } static inline u32 gr_status_r(void) { - return 0x00400700; + return 0x00400700U; } static inline u32 gr_status_fe_method_upper_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_status_fe_method_lower_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_status_fe_method_lower_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_status_fe_gi_v(u32 r) { - return (r >> 21) & 0x1; + return (r >> 21U) & 0x1U; } static inline u32 gr_status_mask_r(void) { - return 0x00400610; + return 0x00400610U; } static inline u32 gr_status_1_r(void) { - return 0x00400604; + return 0x00400604U; } static inline u32 gr_status_2_r(void) { - return 0x00400608; + return 0x00400608U; } static inline u32 gr_engine_status_r(void) { - return 0x0040060c; + return 0x0040060cU; } static inline u32 gr_engine_status_value_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_be0_becs_be_exception_r(void) { - return 0x00410204; + return 0x00410204U; } static inline u32 gr_pri_be0_becs_be_exception_en_r(void) { - return 0x00410208; + return 0x00410208U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) { - return 0x00502c94; + return 0x00502c94U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_activity_0_r(void) { - return 0x00400380; + return 0x00400380U; } static inline u32 gr_activity_1_r(void) { - return 0x00400384; + return 0x00400384U; } static inline u32 gr_activity_2_r(void) { - return 0x00400388; + return 0x00400388U; } static inline u32 gr_activity_4_r(void) { - return 0x00400390; + return 0x00400390U; } static inline u32 gr_activity_4_gpc0_s(void) { - return 3; + return 3U; } static inline u32 gr_activity_4_gpc0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_activity_4_gpc0_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 gr_activity_4_gpc0_v(u32 r) { - return (r >> 0) & 0x7; + return (r >> 0U) & 0x7U; } static inline u32 gr_activity_4_gpc0_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_activity_4_gpc0_preempted_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pri_gpc0_gcc_dbg_r(void) { - return 0x00501000; + return 0x00501000U; } static inline u32 gr_pri_gpcs_gcc_dbg_r(void) { - return 0x00419000; + return 0x00419000U; } static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { - return 0x0050433c; + return 0x0050433cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) { - return 0x00419b3c; + return 0x00419b3cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_sked_activity_r(void) { - return 0x00407054; + return 0x00407054U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) { - return 0x00502c80; + return 0x00502c80U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) { - return 0x00502c84; + return 0x00502c84U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) { - return 0x00502c88; + return 0x00502c88U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) { - return 0x00502c8c; + return 0x00502c8cU; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x00504500; + return 0x00504500U; } static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x00504d00; + return 0x00504d00U; } static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00501d00; + return 0x00501d00U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) { - return 0x0041ac80; + return 0x0041ac80U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) { - return 0x0041ac84; + return 0x0041ac84U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) { - return 0x0041ac88; + return 0x0041ac88U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) { - return 0x0041ac8c; + return 0x0041ac8cU; } static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x0041c500; + return 0x0041c500U; } static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x0041cd00; + return 0x0041cd00U; } static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00419d00; + return 0x00419d00U; } static inline u32 gr_pri_be0_becs_be_activity0_r(void) { - return 0x00410200; + return 0x00410200U; } static inline u32 gr_pri_be1_becs_be_activity0_r(void) { - return 0x00410600; + return 0x00410600U; } static inline u32 gr_pri_bes_becs_be_activity0_r(void) { - return 0x00408a00; + return 0x00408a00U; } static inline u32 gr_pri_ds_mpipe_status_r(void) { - return 0x00405858; + return 0x00405858U; } static inline u32 gr_pri_fe_go_idle_info_r(void) { - return 0x00404194; + return 0x00404194U; } static inline u32 gr_pri_fe_chip_def_info_r(void) { - return 0x00404030; + return 0x00404030U; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { - return 0x00504238; + return 0x00504238U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { - return 0x00504358; + return 0x00504358U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 26) & 0x1; + return (r >> 26U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) { - return 0x0050435c; + return 0x0050435cU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) { - return 0x00504360; + return 0x00504360U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) { - return 0x0050436c; + return 0x0050436cU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) { - return 0x00504370; + return 0x00504370U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) { - return 0x00504374; + return 0x00504374U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) { - return 0x00504638; + return 0x00504638U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 18) & 0x1; + return (r >> 18U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) { - return 0x0050463c; + return 0x0050463cU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) { - return 0x00504640; + return 0x00504640U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { - return 0x005042c4; + return 0x005042c4U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) { - return 0x00504430; + return 0x00504430U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) { - return 0x00504434; + return 0x00504434U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_pri_be0_crop_status1_r(void) { - return 0x00410134; + return 0x00410134U; } static inline u32 gr_pri_bes_crop_status1_r(void) { - return 0x00408934; + return 0x00408934U; } static inline u32 gr_pri_be0_zrop_status_r(void) { - return 0x00410048; + return 0x00410048U; } static inline u32 gr_pri_be0_zrop_status2_r(void) { - return 0x0041004c; + return 0x0041004cU; } static inline u32 gr_pri_bes_zrop_status_r(void) { - return 0x00408848; + return 0x00408848U; } static inline u32 gr_pri_bes_zrop_status2_r(void) { - return 0x0040884c; + return 0x0040884cU; } static inline u32 gr_pipe_bundle_address_r(void) { - return 0x00400200; + return 0x00400200U; } static inline u32 gr_pipe_bundle_address_value_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pipe_bundle_address_veid_f(u32 v) { - return (v & 0x3f) << 20; + return (v & 0x3fU) << 20U; } static inline u32 gr_pipe_bundle_address_veid_w(void) { - return 0; + return 0U; } static inline u32 gr_pipe_bundle_data_r(void) { - return 0x00400204; + return 0x00400204U; } static inline u32 gr_pipe_bundle_config_r(void) { - return 0x00400208; + return 0x00400208U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fe_hww_esr_r(void) { - return 0x00404000; + return 0x00404000U; } static inline u32 gr_fe_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_fe_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { - return 0x00419eac; + return 0x00419eacU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) { - return 0x0050472c; + return 0x0050472cU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) { - return 0x00419eb4; + return 0x00419eb4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) { - return 0x00504734; + return 0x00504734U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fe_go_idle_timeout_r(void) { - return 0x00404154; + return 0x00404154U; } static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) { - return 0x1800; + return 0x1800U; } static inline u32 gr_fe_object_table_r(u32 i) { - return 0x00404200 + i*4; + return 0x00404200U + i*4U; } static inline u32 gr_fe_object_table_nvclass_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fe_tpc_fs_r(u32 i) { - return 0x0040a200 + i*4; + return 0x0040a200U + i*4U; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { - return 0x00404488; + return 0x00404488U; } static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pri_mme_shadow_raw_data_r(void) { - return 0x0040448c; + return 0x0040448cU; } static inline u32 gr_mme_hww_esr_r(void) { - return 0x00404490; + return 0x00404490U; } static inline u32 gr_mme_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_mme_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_memfmt_hww_esr_r(void) { - return 0x00404600; + return 0x00404600U; } static inline u32 gr_memfmt_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_memfmt_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fecs_cpuctl_r(void) { - return 0x00409100; + return 0x00409100U; } static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_cpuctl_alias_r(void) { - return 0x00409130; + return 0x00409130U; } static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_dmactl_r(void) { - return 0x0040910c; + return 0x0040910cU; } static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_fecs_os_r(void) { - return 0x00409080; + return 0x00409080U; } static inline u32 gr_fecs_idlestate_r(void) { - return 0x0040904c; + return 0x0040904cU; } static inline u32 gr_fecs_mailbox0_r(void) { - return 0x00409040; + return 0x00409040U; } static inline u32 gr_fecs_mailbox1_r(void) { - return 0x00409044; + return 0x00409044U; } static inline u32 gr_fecs_irqstat_r(void) { - return 0x00409008; + return 0x00409008U; } static inline u32 gr_fecs_irqmode_r(void) { - return 0x0040900c; + return 0x0040900cU; } static inline u32 gr_fecs_irqmask_r(void) { - return 0x00409018; + return 0x00409018U; } static inline u32 gr_fecs_irqdest_r(void) { - return 0x0040901c; + return 0x0040901cU; } static inline u32 gr_fecs_curctx_r(void) { - return 0x00409050; + return 0x00409050U; } static inline u32 gr_fecs_nxtctx_r(void) { - return 0x00409054; + return 0x00409054U; } static inline u32 gr_fecs_engctl_r(void) { - return 0x004090a4; + return 0x004090a4U; } static inline u32 gr_fecs_debug1_r(void) { - return 0x00409090; + return 0x00409090U; } static inline u32 gr_fecs_debuginfo_r(void) { - return 0x00409094; + return 0x00409094U; } static inline u32 gr_fecs_icd_cmd_r(void) { - return 0x00409200; + return 0x00409200U; } static inline u32 gr_fecs_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_fecs_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 gr_fecs_icd_rdata_r(void) { - return 0x0040920c; + return 0x0040920cU; } static inline u32 gr_fecs_imemc_r(u32 i) { - return 0x00409180 + i*16; + return 0x00409180U + i*16U; } static inline u32 gr_fecs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_imemd_r(u32 i) { - return 0x00409184 + i*16; + return 0x00409184U + i*16U; } static inline u32 gr_fecs_imemt_r(u32 i) { - return 0x00409188 + i*16; + return 0x00409188U + i*16U; } static inline u32 gr_fecs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_dmemc_r(u32 i) { - return 0x004091c0 + i*8; + return 0x004091c0U + i*8U; } static inline u32 gr_fecs_dmemc_offs_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 gr_fecs_dmemc_offs_v(u32 r) { - return (r >> 2) & 0x3f; + return (r >> 2U) & 0x3fU; } static inline u32 gr_fecs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_dmemd_r(u32 i) { - return 0x004091c4 + i*8; + return 0x004091c4U + i*8U; } static inline u32 gr_fecs_dmatrfbase_r(void) { - return 0x00409110; + return 0x00409110U; } static inline u32 gr_fecs_dmatrfmoffs_r(void) { - return 0x00409114; + return 0x00409114U; } static inline u32 gr_fecs_dmatrffboffs_r(void) { - return 0x0040911c; + return 0x0040911cU; } static inline u32 gr_fecs_dmatrfcmd_r(void) { - return 0x00409118; + return 0x00409118U; } static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_fecs_bootvec_r(void) { - return 0x00409104; + return 0x00409104U; } static inline u32 gr_fecs_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_falcon_hwcfg_r(void) { - return 0x00409108; + return 0x00409108U; } static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) { - return 0x0041a108; + return 0x0041a108U; } static inline u32 gr_fecs_falcon_rm_r(void) { - return 0x00409084; + return 0x00409084U; } static inline u32 gr_fecs_current_ctx_r(void) { - return 0x00409b00; + return 0x00409b00U; } static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_current_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_current_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_current_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_current_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 gr_fecs_current_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_current_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_current_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_current_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_current_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_method_data_r(void) { - return 0x00409500; + return 0x00409500U; } static inline u32 gr_fecs_method_push_r(void) { - return 0x00409504; + return 0x00409504U; } static inline u32 gr_fecs_method_push_adr_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) { - return 0x3; + return 0x3U; } static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { - return 0x21; + return 0x21U; } static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gr_fecs_host_int_status_r(void) { - return 0x00409c18; + return 0x00409c18U; } static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_host_int_clear_r(void) { - return 0x00409c20; + return 0x00409c20U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_r(void) { - return 0x00409c24; + return 0x00409c24U; } static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) { - return 0x00409614; + return 0x00409614U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) { - return 0x0040960c; + return 0x0040960cU; } static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) { - return 0x00409800 + i*4; + return 0x00409800U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) { - return 0x004098c0 + i*4; + return 0x004098c0U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) { - return 0x00409840 + i*4; + return 0x00409840U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_fs_r(void) { - return 0x00409604; + return 0x00409604U; } static inline u32 gr_fecs_fs_num_available_gpcs_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_fs_num_available_fbps_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_m(void) { - return 0x1f << 16; + return 0x1fU << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_fecs_cfg_r(void) { - return 0x00409620; + return 0x00409620U; } static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_fecs_rc_lanes_r(void) { - return 0x00409880; + return 0x00409880U; } static inline u32 gr_fecs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_fecs_ctxsw_status_1_r(void) { - return 0x00409400; + return 0x00409400U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_adr_r(void) { - return 0x00409a24; + return 0x00409a24U; } static inline u32 gr_fecs_new_ctx_r(void) { - return 0x00409b04; + return 0x00409b04U; } static inline u32 gr_fecs_new_ctx_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_new_ctx_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_new_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_new_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_new_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_new_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_new_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_new_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_new_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_new_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_ptr_r(void) { - return 0x00409a0c; + return 0x00409a0cU; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_arb_ctx_cmd_r(void) { - return 0x00409a10; + return 0x00409a10U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) { - return 0x00409c00; + return 0x00409c00U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) { - return 0x00502c04; + return 0x00502c04U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) { - return 0x00502400; + return 0x00502400U; } static inline u32 gr_fecs_ctxsw_idlestate_r(void) { - return 0x00409420; + return 0x00409420U; } static inline u32 gr_fecs_feature_override_ecc_r(void) { - return 0x00409658; + return 0x00409658U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { - return 0x00502420; + return 0x00502420U; } static inline u32 gr_rstr2d_gpc_map_r(u32 i) { - return 0x0040780c + i*4; + return 0x0040780cU + i*4U; } static inline u32 gr_rstr2d_map_table_cfg_r(void) { - return 0x004078bc; + return 0x004078bcU; } static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_hww_esr_r(void) { - return 0x00406018; + return 0x00406018U; } static inline u32 gr_pd_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pd_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) { - return 0x00406028 + i*4; + return 0x00406028U + i*4U; } static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) { - return (v & 0xf) << 24; + return (v & 0xfU) << 24U; } static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) { - return (v & 0xf) << 28; + return (v & 0xfU) << 28U; } static inline u32 gr_pd_ab_dist_cfg0_r(void) { - return 0x004064c0; + return 0x004064c0U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pd_ab_dist_cfg1_r(void) { - return 0x004064c4; + return 0x004064c4U; } static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) { - return 0xffff; + return 0xffffU; } static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gr_pd_ab_dist_cfg2_r(void) { - return 0x004064c8; + return 0x004064c8U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) { - return (v & 0x1fff) << 0; + return (v & 0x1fffU) << 0U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) { - return 0x00001680; + return 0x00001680U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) { - return (v & 0x1fff) << 16; + return (v & 0x1fffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { - return 0x00001680; + return 0x00001680U; } static inline u32 gr_pd_dist_skip_table_r(u32 i) { - return 0x004064d0 + i*4; + return 0x004064d0U + i*4U; } static inline u32 gr_pd_dist_skip_table__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_ds_debug_r(void) { - return 0x00405800; + return 0x00405800U; } static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 gr_ds_zbc_color_r_r(void) { - return 0x00405804; + return 0x00405804U; } static inline u32 gr_ds_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_g_r(void) { - return 0x00405808; + return 0x00405808U; } static inline u32 gr_ds_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_b_r(void) { - return 0x0040580c; + return 0x0040580cU; } static inline u32 gr_ds_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_a_r(void) { - return 0x00405810; + return 0x00405810U; } static inline u32 gr_ds_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_r(void) { - return 0x00405814; + return 0x00405814U; } static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) { - return (v & 0x7f) << 0; + return (v & 0x7fU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gr_ds_zbc_z_r(void) { - return 0x00405818; + return 0x00405818U; } static inline u32 gr_ds_zbc_z_val_s(void) { - return 32; + return 32U; } static inline u32 gr_ds_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_z_val_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_ds_zbc_z_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_ds_zbc_z_val__init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_ds_zbc_z_val__init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_r(void) { - return 0x0040581c; + return 0x0040581cU; } static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_tbl_index_r(void) { - return 0x00405820; + return 0x00405820U; } static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_ds_zbc_tbl_ld_r(void) { - return 0x00405824; + return 0x00405824U; } static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_tga_constraintlogic_beta_r(void) { - return 0x00405830; + return 0x00405830U; } static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) { - return 0x0040585c; + return 0x0040585cU; } static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_ds_hww_esr_r(void) { - return 0x00405840; + return 0x00405840U; } static inline u32 gr_ds_hww_esr_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_esr_2_r(void) { - return 0x00405848; + return 0x00405848U; } static inline u32 gr_ds_hww_esr_2_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_2_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_2_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_2_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_report_mask_r(void) { - return 0x00405844; + return 0x00405844U; } static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_ds_hww_report_mask_2_r(void) { - return 0x0040584c; + return 0x0040584cU; } static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) { - return 0x00405870 + i*4; + return 0x00405870U + i*4U; } static inline u32 gr_scc_bundle_cb_base_r(void) { - return 0x00408004; + return 0x00408004U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_bundle_cb_size_r(void) { - return 0x00408008; + return 0x00408008U; } static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_pagepool_base_r(void) { - return 0x0040800c; + return 0x0040800cU; } static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_pagepool_r(void) { - return 0x00408010; + return 0x00408010U; } static inline u32 gr_scc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_pagepool_max_valid_pages_s(void) { - return 10; + return 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) { - return (v & 0x3ff) << 10; + return (v & 0x3ffU) << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_m(void) { - return 0x3ff << 10; + return 0x3ffU << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) { - return (r >> 10) & 0x3ff; + return (r >> 10U) & 0x3ffU; } static inline u32 gr_scc_pagepool_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_init_r(void) { - return 0x0040802c; + return 0x0040802cU; } static inline u32 gr_scc_init_ram_trigger_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_scc_hww_esr_r(void) { - return 0x00408030; + return 0x00408030U; } static inline u32 gr_scc_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_scc_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_sked_hww_esr_r(void) { - return 0x00407020; + return 0x00407020U; } static inline u32 gr_sked_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_sked_hww_esr_en_r(void) { - return 0x00407024; + return 0x00407024U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) { - return 0x1 << 25; + return 0x1U << 25U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 gr_cwd_fs_r(void) { - return 0x00405b00; + return 0x00405b00U; } static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) { - return 0x00405b60 + i*4; + return 0x00405b60U + i*4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_cwd_sm_id_r(u32 i) { - return 0x00405ba0 + i*4; + return 0x00405ba0U + i*4U; } static inline u32 gr_cwd_sm_id__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpc0_fs_gpc_r(void) { - return 0x00502608; + return 0x00502608U; } static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_gpc0_cfg_r(void) { - return 0x00502620; + return 0x00502620U; } static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpccs_rc_lanes_r(void) { - return 0x00502880; + return 0x00502880U; } static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_rc_lane_size_r(void) { - return 0x00502910; + return 0x00502910U; } static inline u32 gr_gpccs_rc_lane_size_v_s(void) { - return 24; + return 24U; } static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_zcull_fs_r(void) { - return 0x00500910; + return 0x00500910U; } static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_gpc0_zcull_ram_addr_r(void) { - return 0x00500914; + return 0x00500914U; } static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) { - return 0x00500918; + return 0x00500918U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) { - return 0x00800000; + return 0x00800000U; } static inline u32 gr_gpc0_zcull_total_ram_size_r(void) { - return 0x00500920; + return 0x00500920U; } static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) { - return 0x00500a04 + i*32; + return 0x00500a04U + i*32U; } static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) { - return 0x00500c10 + i*4; + return 0x00500c10U + i*4U; } static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) { - return 0x00500c30 + i*4; + return 0x00500c30U + i*4U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) { - return 0x00504088; + return 0x00504088U; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { - return 0x00504608; + return 0x00504608U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { - return 0x00504330; + return 0x00504330U; } static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) { - return (r >> 8) & 0xfff; + return (r >> 8U) & 0xfffU; } static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) { - return (r >> 20) & 0xfff; + return (r >> 20U) & 0xfffU; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) { - return 0x00503018; + return 0x00503018U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) { - return 0x005030c0; + return 0x005030c0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000480; + return 0x00000480U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00000d10; + return 0x00000d10U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) { - return 0x005030f4; + return 0x005030f4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) { - return 0x005030e4; + return 0x005030e4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) { - return 0x005030f8; + return 0x005030f8U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) { - return 0x005030f0; + return 0x005030f0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000480; + return 0x00000480U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { - return 0x00419e00; + return 0x00419e00U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) { - return 0x00419e04; + return 0x00419e04U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) { - return 21; + return 21U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) { - return (v & 0x1fffff) << 0; + return (v & 0x1fffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) { - return 0x1fffff << 0; + return 0x1fffffU << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) { - return (r >> 0) & 0x1fffff; + return (r >> 0U) & 0x1fffffU; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpccs_falcon_addr_r(void) { - return 0x0041a0ac; + return 0x0041a0acU; } static inline u32 gr_gpccs_falcon_addr_lsb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_msb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) { - return (r >> 6) & 0x3f; + return (r >> 6U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_ext_s(void) { - return 12; + return 12U; } static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_m(void) { - return 0xfff << 0; + return 0xfffU << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_gpccs_cpuctl_r(void) { - return 0x0041a100; + return 0x0041a100U; } static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpccs_dmactl_r(void) { - return 0x0041a10c; + return 0x0041a10cU; } static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpccs_imemc_r(u32 i) { - return 0x0041a180 + i*16; + return 0x0041a180U + i*16U; } static inline u32 gr_gpccs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_imemd_r(u32 i) { - return 0x0041a184 + i*16; + return 0x0041a184U + i*16U; } static inline u32 gr_gpccs_imemt_r(u32 i) { - return 0x0041a188 + i*16; + return 0x0041a188U + i*16U; } static inline u32 gr_gpccs_imemt__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_gpccs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpccs_dmemc_r(u32 i) { - return 0x0041a1c0 + i*8; + return 0x0041a1c0U + i*8U; } static inline u32 gr_gpccs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_dmemd_r(u32 i) { - return 0x0041a1c4 + i*8; + return 0x0041a1c4U + i*8U; } static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) { - return 0x0041a800 + i*4; + return 0x0041a800U + i*4U; } static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) { - return 0x00418e24; + return 0x00418e24U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) { - return 32; + return 32U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) { - return 0x00418e28; + return 0x00418e28U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) { - return 11; + return 11U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) { - return 0x7ff << 0; + return 0x7ffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) { - return (r >> 0) & 0x7ff; + return (r >> 0U) & 0x7ffU; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) { - return 0x30; + return 0x30U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) { - return 0x005001dc; + return 0x005001dcU; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { - return 0x000004b0; + return 0x000004b0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { - return 0x005001d8; + return 0x005001d8U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) { - return 0x004181e4; + return 0x004181e4U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) { - return 0x0041befc; + return 0x0041befcU; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) { - return 0x00418ea0 + i*4; + return 0x00418ea0U + i*4U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) { - return 0x00418010 + i*4; + return 0x00418010U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) { - return 0x0041804c + i*4; + return 0x0041804cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) { - return 0x00418088 + i*4; + return 0x00418088U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) { - return 0x004180c4 + i*4; + return 0x004180c4U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) { - return 0x00418100; + return 0x00418100U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) { - return 0x00418110 + i*4; + return 0x00418110U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) { - return 0x0041814c; + return 0x0041814cU; } static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) { - return 0x0041815c + i*4; + return 0x0041815cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) { - return 0x00418198; + return 0x00418198U; } static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { - return 0x00418810; + return 0x00418810U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_crstr_gpc_map_r(u32 i) { - return 0x00418b08 + i*4; + return 0x00418b08U + i*4U; } static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) { - return (v & 0x1f) << 5; + return (v & 0x1fU) << 5U; } static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) { - return (v & 0x1f) << 10; + return (v & 0x1fU) << 10U; } static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) { - return (v & 0x1f) << 20; + return (v & 0x1fU) << 20U; } static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) { - return (v & 0x1f) << 25; + return (v & 0x1fU) << 25U; } static inline u32 gr_crstr_map_table_cfg_r(void) { - return 0x00418bb8; + return 0x00418bb8U; } static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) { - return 0x00418980 + i*4; + return 0x00418980U + i*4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) { - return (v & 0x7) << 4; + return (v & 0x7U) << 4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) { - return (v & 0x7) << 16; + return (v & 0x7U) << 16U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x7U) << 20U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) { - return (v & 0x7) << 28; + return (v & 0x7U) << 28U; } static inline u32 gr_gpcs_gpm_pd_cfg_r(void) { - return 0x00418c6c; + return 0x00418c6cU; } static inline u32 gr_gpcs_gcc_pagepool_base_r(void) { - return 0x00419004; + return 0x00419004U; } static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_gcc_pagepool_r(void) { - return 0x00419008; + return 0x00419008U; } static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) { - return 0x0041980c; + return 0x0041980cU; } static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) { - return 0x00419848; + return 0x00419848U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) { - return 0x00419c00; + return 0x00419c00U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) { - return 0x00419c2c; + return 0x00419c2cU; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419ea8; + return 0x00419ea8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) { - return 0x00504728; + return 0x00504728U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { - return 0x00419d0c; + return 0x00419d0cU; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { - return 0x0041ac94; + return 0x0041ac94U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { - return 0x00504704; + return 0x00504704U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) { - return 0x00504708; + return 0x00504708U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) { - return 0x0050470c; + return 0x0050470cU; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) { - return 0x00504710; + return 0x00504710U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) { - return 0x00504714; + return 0x00504714U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) { - return 0x00504718; + return 0x00504718U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) { - return 0x0050471c; + return 0x0050471cU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) { - return 0x00419e90; + return 0x00419e90U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) { - return 0x00419e94; + return 0x00419e94U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) { - return 0x00419e80; + return 0x00419e80U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { - return 0x00504700; + return 0x00504700U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { - return 0x00504730; + return 0x00504730U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) { - return 0xf << 24; + return 0xfU << 24U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) { - return 0x0050460c; + return 0x0050460cU; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { - return 0x00504738; + return 0x00504738U; } static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { - return 0x005043a0; + return 0x005043a0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) { - return 0x00419ba0; + return 0x00419ba0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) { - return 0x005043b0; + return 0x005043b0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) { - return 0x00419bb0; + return 0x00419bb0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) { - return 0x0041be08; + return 0x0041be08U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) { - return 0x0041bf00 + i*4; + return 0x0041bf00U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { - return 0x0041bfd0; + return 0x0041bfd0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) { - return (v & 0x7) << 21; + return (v & 0x7U) << 21U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) { - return 0x0041bfd4; + return 0x0041bfd4U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) { - return 0x0041bfb0 + i*4; + return 0x0041bfb0U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_bes_zrop_settings_r(void) { - return 0x00408850; + return 0x00408850U; } static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_be0_crop_debug3_r(void) { - return 0x00410108; + return 0x00410108U; } static inline u32 gr_bes_crop_debug3_r(void) { - return 0x00408908; + return 0x00408908U; } static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_bes_crop_settings_r(void) { - return 0x00408958; + return 0x00408958U; } static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gr_zcull_subregion_qty_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) { - return 0x00419a00; + return 0x00419a00U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) { - return 0x00419bf0; + return 0x00419bf0U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fe_pwr_mode_r(void) { - return 0x00404170; + return 0x00404170U; } static inline u32 gr_fe_pwr_mode_mode_auto_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fe_pwr_mode_req_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_fe_pwr_mode_req_send_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fe_pwr_mode_req_done_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) { - return 0x00418880; + return 0x00418880U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) { - return 0x3 << 3; + return 0x3U << 3U; } static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) { - return 0x3 << 5; + return 0x3U << 5U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { - return 0x00418890; + return 0x00418890U; } static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) { - return 0x00418894; + return 0x00418894U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) { - return 0x004188b0; + return 0x004188b0U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) { - return 0x004188b4; + return 0x004188b4U; } static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) { - return 0x004188b8; + return 0x004188b8U; } static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { - return 0x004188ac; + return 0x004188acU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419e84; + return 0x00419e84U; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { - return 0x004041c0; + return 0x004041c0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) { - return 0x00419bd8; + return 0x00419bd8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) { - return 0x7 << 8; + return 0x7U << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) { - return 0x00419ba4; + return 0x00419ba4U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { - return 0x3 << 11; + return 0x3U << 11U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_gpcs_tc_debug0_r(void) { - return 0x00418708; + return 0x00418708U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0x1ff << 0; + return 0x1ffU << 0U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h index b5fc4b63..3543f0b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -58,562 +58,562 @@ static inline u32 ltc_pltcg_base_v(void) { - return 0x00140000; + return 0x00140000U; } static inline u32 ltc_pltcg_extent_v(void) { - return 0x0017ffff; + return 0x0017ffffU; } static inline u32 ltc_ltc0_ltss_v(void) { - return 0x00140200; + return 0x00140200U; } static inline u32 ltc_ltc0_lts0_v(void) { - return 0x00140400; + return 0x00140400U; } static inline u32 ltc_ltcs_ltss_v(void) { - return 0x0017e200; + return 0x0017e200U; } static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) { - return 0x00140518; + return 0x00140518U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) { - return 0x0017e318; + return 0x0017e318U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) { - return 0x00140494; + return 0x00140494U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) { - return (r >> 16) & 0x3; + return (r >> 16U) & 0x3U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) { - return 0x0017e26c; + return 0x0017e26cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) { - return 0x2; + return 0x2U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) { - return 0x0017e270; + return 0x0017e270U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { - return 0x0017e274; + return 0x0017e274U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { - return 0x0003ffff; + return 0x0003ffffU; } static inline u32 ltc_ltcs_ltss_cbc_base_r(void) { - return 0x0017e278; + return 0x0017e278U; } static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) { - return (r >> 0) & 0x3ffffff; + return (r >> 0U) & 0x3ffffffU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { - return 0x0017e27c; + return 0x0017e27cU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) { - return (r >> 25) & 0x1; + return (r >> 25U) & 0x1U; } static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { - return 0x0017e000; + return 0x0017e000U; } static inline u32 ltc_ltcs_ltss_cbc_param_r(void) { - return 0x0017e280; + return 0x0017e280U; } static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) { - return (r >> 28) & 0xf; + return (r >> 28U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) { - return 0x0017e3f4; + return 0x0017e3f4U; } static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) { - return 0x0017e2ac; + return 0x0017e2acU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) { - return 0x0017e338; + return 0x0017e338U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) { - return 0x0017e33c + i*4; + return 0x0017e33cU + i*4U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) { - return 0x0017e34c; + return 0x0017e34cU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) { - return 32; + return 32U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) { - return 0x0017e204; + return 0x0017e204U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) { - return 8; + return 8U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) { - return 0x0017e2b0; + return 0x0017e2b0U; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_g_elpg_r(void) { - return 0x0017e214; + return 0x0017e214U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_r(void) { - return 0x00140214; + return 0x00140214U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_r(void) { - return 0x00142214; + return 0x00142214U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_intr_r(void) { - return 0x0017e20c; + return 0x0017e20cU; } static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 ltc_ltc0_lts0_intr_r(void) { - return 0x0014040c; + return 0x0014040cU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) { - return 0x0014051c; + return 0x0014051cU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) { - return 0x0017e2a0; + return 0x0017e2a0U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) { - return 0x0017e2a4; + return 0x0017e2a4U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) { - return 0x001402a0; + return 0x001402a0U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) { - return 0x001402a4; + return 0x001402a4U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) { - return 0x001422a0; + return 0x001422a0U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) { - return 0x001422a4; + return 0x001422a4U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) { - return 0x0014058c; + return 0x0014058cU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 54bd1e35..2efeac79 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -58,194 +58,194 @@ static inline u32 mc_boot_0_r(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_boot_0_architecture_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 mc_boot_0_implementation_v(u32 r) { - return (r >> 20) & 0xf; + return (r >> 20U) & 0xfU; } static inline u32 mc_boot_0_major_revision_v(u32 r) { - return (r >> 4) & 0xf; + return (r >> 4U) & 0xfU; } static inline u32 mc_boot_0_minor_revision_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 mc_intr_r(u32 i) { - return 0x00000100 + i*4; + return 0x00000100U + i*4U; } static inline u32 mc_intr_pfifo_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_intr_hub_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 mc_intr_pgraph_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_intr_pmu_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 mc_intr_ltc_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 mc_intr_priv_ring_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 mc_intr_pbus_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_intr_en_r(u32 i) { - return 0x00000140 + i*4; + return 0x00000140U + i*4U; } static inline u32 mc_intr_en_set_r(u32 i) { - return 0x00000160 + i*4; + return 0x00000160U + i*4U; } static inline u32 mc_intr_en_clear_r(u32 i) { - return 0x00000180 + i*4; + return 0x00000180U + i*4U; } static inline u32 mc_enable_r(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 mc_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 mc_enable_pmedia_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pmedia_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 mc_enable_pmedia_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 mc_enable_pmedia_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 mc_enable_ce0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 mc_enable_pfifo_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_enable_pgraph_enabled_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_enable_pwr_v(u32 r) { - return (r >> 13) & 0x1; + return (r >> 13U) & 0x1U; } static inline u32 mc_enable_pwr_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_enable_pwr_enabled_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 mc_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_enable_ce2_m(void) { - return 0x1 << 21; + return 0x1U << 21U; } static inline u32 mc_enable_ce2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 mc_enable_blg_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 mc_enable_perfmon_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_intr_ltc_r(void) { - return 0x000001c0; + return 0x000001c0U; } static inline u32 mc_enable_pb_r(void) { - return 0x00000204; + return 0x00000204U; } static inline u32 mc_enable_pb_0_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pb_0_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 mc_enable_pb_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 mc_enable_pb_0_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 mc_enable_pb_0_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 mc_elpg_enable_r(void) { - return 0x0000020c; + return 0x0000020cU; } static inline u32 mc_elpg_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_elpg_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_elpg_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_elpg_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index f0fc0773..2d98b914 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -58,594 +58,594 @@ static inline u32 pbdma_gp_entry1_r(void) { - return 0x10000004; + return 0x10000004U; } static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pbdma_gp_entry1_length_f(u32 v) { - return (v & 0x1fffff) << 10; + return (v & 0x1fffffU) << 10U; } static inline u32 pbdma_gp_entry1_length_v(u32 r) { - return (r >> 10) & 0x1fffff; + return (r >> 10U) & 0x1fffffU; } static inline u32 pbdma_gp_base_r(u32 i) { - return 0x00040048 + i*8192; + return 0x00040048U + i*8192U; } static inline u32 pbdma_gp_base__size_1_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 pbdma_gp_base_offset_f(u32 v) { - return (v & 0x1fffffff) << 3; + return (v & 0x1fffffffU) << 3U; } static inline u32 pbdma_gp_base_rsvd_s(void) { - return 3; + return 3U; } static inline u32 pbdma_gp_base_hi_r(u32 i) { - return 0x0004004c + i*8192; + return 0x0004004cU + i*8192U; } static inline u32 pbdma_gp_base_hi_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 pbdma_gp_fetch_r(u32 i) { - return 0x00040050 + i*8192; + return 0x00040050U + i*8192U; } static inline u32 pbdma_gp_get_r(u32 i) { - return 0x00040014 + i*8192; + return 0x00040014U + i*8192U; } static inline u32 pbdma_gp_put_r(u32 i) { - return 0x00040000 + i*8192; + return 0x00040000U + i*8192U; } static inline u32 pbdma_pb_fetch_r(u32 i) { - return 0x00040054 + i*8192; + return 0x00040054U + i*8192U; } static inline u32 pbdma_pb_fetch_hi_r(u32 i) { - return 0x00040058 + i*8192; + return 0x00040058U + i*8192U; } static inline u32 pbdma_get_r(u32 i) { - return 0x00040018 + i*8192; + return 0x00040018U + i*8192U; } static inline u32 pbdma_get_hi_r(u32 i) { - return 0x0004001c + i*8192; + return 0x0004001cU + i*8192U; } static inline u32 pbdma_put_r(u32 i) { - return 0x0004005c + i*8192; + return 0x0004005cU + i*8192U; } static inline u32 pbdma_put_hi_r(u32 i) { - return 0x00040060 + i*8192; + return 0x00040060U + i*8192U; } static inline u32 pbdma_pb_header_r(u32 i) { - return 0x00040084 + i*8192; + return 0x00040084U + i*8192U; } static inline u32 pbdma_pb_header_priv_user_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_method_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_subchannel_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_level_main_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_pb_header_type_inc_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_pb_header_type_non_inc_f(void) { - return 0x60000000; + return 0x60000000U; } static inline u32 pbdma_hdr_shadow_r(u32 i) { - return 0x00040118 + i*8192; + return 0x00040118U + i*8192U; } static inline u32 pbdma_subdevice_r(u32 i) { - return 0x00040094 + i*8192; + return 0x00040094U + i*8192U; } static inline u32 pbdma_subdevice_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 pbdma_subdevice_status_active_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_subdevice_channel_dma_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_method0_r(u32 i) { - return 0x000400c0 + i*8192; + return 0x000400c0U + i*8192U; } static inline u32 pbdma_method0_fifo_size_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pbdma_method0_addr_f(u32 v) { - return (v & 0xfff) << 2; + return (v & 0xfffU) << 2U; } static inline u32 pbdma_method0_addr_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 pbdma_method0_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 pbdma_method0_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_method0_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_method1_r(u32 i) { - return 0x000400c8 + i*8192; + return 0x000400c8U + i*8192U; } static inline u32 pbdma_method2_r(u32 i) { - return 0x000400d0 + i*8192; + return 0x000400d0U + i*8192U; } static inline u32 pbdma_method3_r(u32 i) { - return 0x000400d8 + i*8192; + return 0x000400d8U + i*8192U; } static inline u32 pbdma_data0_r(u32 i) { - return 0x000400c4 + i*8192; + return 0x000400c4U + i*8192U; } static inline u32 pbdma_acquire_r(u32 i) { - return 0x00040030 + i*8192; + return 0x00040030U + i*8192U; } static inline u32 pbdma_acquire_retry_man_2_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_acquire_retry_exp_2_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_acquire_timeout_exp_f(u32 v) { - return (v & 0xf) << 11; + return (v & 0xfU) << 11U; } static inline u32 pbdma_acquire_timeout_exp_max_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 pbdma_acquire_timeout_exp_max_f(void) { - return 0x7800; + return 0x7800U; } static inline u32 pbdma_acquire_timeout_man_f(u32 v) { - return (v & 0xffff) << 15; + return (v & 0xffffU) << 15U; } static inline u32 pbdma_acquire_timeout_man_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 pbdma_acquire_timeout_man_max_f(void) { - return 0x7fff8000; + return 0x7fff8000U; } static inline u32 pbdma_acquire_timeout_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_acquire_timeout_en_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_status_r(u32 i) { - return 0x00040100 + i*8192; + return 0x00040100U + i*8192U; } static inline u32 pbdma_channel_r(u32 i) { - return 0x00040120 + i*8192; + return 0x00040120U + i*8192U; } static inline u32 pbdma_signature_r(u32 i) { - return 0x00040010 + i*8192; + return 0x00040010U + i*8192U; } static inline u32 pbdma_signature_hw_valid_f(void) { - return 0xface; + return 0xfaceU; } static inline u32 pbdma_signature_sw_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_r(u32 i) { - return 0x00040008 + i*8192; + return 0x00040008U + i*8192U; } static inline u32 pbdma_userd_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 pbdma_userd_addr_f(u32 v) { - return (v & 0x7fffff) << 9; + return (v & 0x7fffffU) << 9U; } static inline u32 pbdma_config_r(u32 i) { - return 0x000400f4 + i*8192; + return 0x000400f4U + i*8192U; } static inline u32 pbdma_config_l2_evict_first_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_l2_evict_normal_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_config_l2_evict_last_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_config_ce_split_enable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_ce_split_disable_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_config_auth_level_non_privileged_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_auth_level_privileged_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_config_userd_writeback_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_userd_writeback_enable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_userd_hi_r(u32 i) { - return 0x0004000c + i*8192; + return 0x0004000cU + i*8192U; } static inline u32 pbdma_userd_hi_addr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_hce_ctrl_r(u32 i) { - return 0x000400e4 + i*8192; + return 0x000400e4U + i*8192U; } static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_r(u32 i) { - return 0x00040108 + i*8192; + return 0x00040108U + i*8192U; } static inline u32 pbdma_intr_0_memreq_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pbdma_intr_0_memreq_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_intr_0_memack_extra_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_intr_0_memflush_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_memop_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 pbdma_intr_0_lbconnect_pending_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_intr_0_lbreq_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 pbdma_intr_0_lback_extra_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_intr_0_gpfifo_pending_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 pbdma_intr_0_gpptr_pending_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 pbdma_intr_0_gpentry_pending_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 pbdma_intr_0_gpcrc_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_intr_0_pbptr_pending_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_intr_0_pbentry_pending_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 pbdma_intr_0_method_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pbdma_intr_0_methodcrc_pending_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_intr_0_device_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 pbdma_intr_0_eng_reset_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_intr_0_semaphore_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_intr_0_acquire_pending_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 pbdma_intr_0_pri_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_intr_0_pbseg_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 pbdma_intr_0_signature_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_1_r(u32 i) { - return 0x00040148 + i*8192; + return 0x00040148U + i*8192U; } static inline u32 pbdma_intr_1_ctxnotvalid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_en_0_r(u32 i) { - return 0x0004010c + i*8192; + return 0x0004010cU + i*8192U; } static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_en_1_r(u32 i) { - return 0x0004014c + i*8192; + return 0x0004014cU + i*8192U; } static inline u32 pbdma_intr_stall_r(u32 i) { - return 0x0004013c + i*8192; + return 0x0004013cU + i*8192U; } static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_stall_1_r(u32 i) { - return 0x00040140 + i*8192; + return 0x00040140U + i*8192U; } static inline u32 pbdma_udma_nop_r(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pbdma_runlist_timeslice_r(u32 i) { - return 0x000400f8 + i*8192; + return 0x000400f8U + i*8192U; } static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) { - return 0x3000; + return 0x3000U; } static inline u32 pbdma_runlist_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_target_r(u32 i) { - return 0x000400ac + i*8192; + return 0x000400acU + i*8192U; } static inline u32 pbdma_target_engine_sw_f(void) { - return 0x1f; + return 0x1fU; } static inline u32 pbdma_target_eng_ctx_valid_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_target_eng_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_ce_ctx_valid_true_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_target_ce_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 pbdma_target_should_send_tsg_event_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_target_should_send_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_r(u32 i) { - return 0x000400fc + i*8192; + return 0x000400fcU + i*8192U; } static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_set_channel_info_veid_f(u32 v) { - return (v & 0x3f) << 8; + return (v & 0x3fU) << 8U; } static inline u32 pbdma_timeout_r(u32 i) { - return 0x0004012c + i*8192; + return 0x0004012cU + i*8192U; } static inline u32 pbdma_timeout_period_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 pbdma_timeout_period_max_f(void) { - return 0xffffffff; + return 0xffffffffU; } static inline u32 pbdma_timeout_period_init_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index d9c8a348..4fbe37cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -58,154 +58,154 @@ static inline u32 perf_pmasys_control_r(void) { - return 0x0024a000; + return 0x0024a000U; } static inline u32 perf_pmasys_control_membuf_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) { - return 0x10; + return 0x10U; } static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) { - return 0x20; + return 0x20U; } static inline u32 perf_pmasys_mem_block_r(void) { - return 0x0024a070; + return 0x0024a070U; } static inline u32 perf_pmasys_mem_block_base_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 perf_pmasys_mem_block_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 perf_pmasys_mem_block_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 perf_pmasys_mem_block_target_lfb_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_target_lfb_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 perf_pmasys_mem_block_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 perf_pmasys_mem_block_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 perf_pmasys_mem_block_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_mem_block_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 perf_pmasys_mem_block_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_outbase_r(void) { - return 0x0024a074; + return 0x0024a074U; } static inline u32 perf_pmasys_outbase_ptr_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_outbaseupper_r(void) { - return 0x0024a078; + return 0x0024a078U; } static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 perf_pmasys_outsize_r(void) { - return 0x0024a07c; + return 0x0024a07cU; } static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_mem_bytes_r(void) { - return 0x0024a084; + return 0x0024a084U; } static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_mem_bump_r(void) { - return 0x0024a088; + return 0x0024a088U; } static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_enginestatus_r(void) { - return 0x0024a0a4; + return 0x0024a0a4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h index 3250bf3e..8f005a22 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -58,6 +58,6 @@ static inline u32 pram_data032_r(u32 i) { - return 0x00700000 + i*4; + return 0x00700000U + i*4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h index ca9da11d..5eca93cc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -58,110 +58,110 @@ static inline u32 pri_ringmaster_command_r(void) { - return 0x0012004c; + return 0x0012004cU; } static inline u32 pri_ringmaster_command_cmd_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 pri_ringmaster_command_cmd_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) { - return 0x2; + return 0x2U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) { - return 0x3; + return 0x3U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_command_data_r(void) { - return 0x00120048; + return 0x00120048U; } static inline u32 pri_ringmaster_start_results_r(void) { - return 0x00120050; + return 0x00120050U; } static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pri_ringmaster_intr_status0_r(void) { - return 0x00120058; + return 0x00120058U; } static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 pri_ringmaster_intr_status1_r(void) { - return 0x0012005c; + return 0x0012005cU; } static inline u32 pri_ringmaster_global_ctl_r(void) { - return 0x00120060; + return 0x00120060U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_enum_fbp_r(void) { - return 0x00120074; + return 0x00120074U; } static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_gpc_r(void) { - return 0x00120078; + return 0x00120078U; } static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_ltc_r(void) { - return 0x0012006c; + return 0x0012006cU; } static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h index 70cf0461..fc522d51 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -58,22 +58,22 @@ static inline u32 pri_ringstation_gpc_master_config_r(u32 i) { - return 0x00128300 + i*4; + return 0x00128300U + i*4U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) { - return 0x00128120; + return 0x00128120U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) { - return 0x00128124; + return 0x00128124U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) { - return 0x00128128; + return 0x00128128U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) { - return 0x0012812c; + return 0x0012812cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h index 741e5bc2..885ea30a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -58,34 +58,34 @@ static inline u32 pri_ringstation_sys_master_config_r(u32 i) { - return 0x00122300 + i*4; + return 0x00122300U + i*4U; } static inline u32 pri_ringstation_sys_decode_config_r(void) { - return 0x00122204; + return 0x00122204U; } static inline u32 pri_ringstation_sys_decode_config_ring_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringstation_sys_priv_error_adr_r(void) { - return 0x00122120; + return 0x00122120U; } static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) { - return 0x00122124; + return 0x00122124U; } static inline u32 pri_ringstation_sys_priv_error_info_r(void) { - return 0x00122128; + return 0x00122128U; } static inline u32 pri_ringstation_sys_priv_error_code_r(void) { - return 0x0012212c; + return 0x0012212cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index ca851cd4..52a7dfc4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -58,110 +58,110 @@ static inline u32 proj_gpc_base_v(void) { - return 0x00500000; + return 0x00500000U; } static inline u32 proj_gpc_shared_base_v(void) { - return 0x00418000; + return 0x00418000U; } static inline u32 proj_gpc_stride_v(void) { - return 0x00008000; + return 0x00008000U; } static inline u32 proj_ltc_stride_v(void) { - return 0x00002000; + return 0x00002000U; } static inline u32 proj_lts_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_fbpa_stride_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_ppc_in_gpc_base_v(void) { - return 0x00003000; + return 0x00003000U; } static inline u32 proj_ppc_in_gpc_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_rop_base_v(void) { - return 0x00410000; + return 0x00410000U; } static inline u32 proj_rop_shared_base_v(void) { - return 0x00408800; + return 0x00408800U; } static inline u32 proj_rop_stride_v(void) { - return 0x00000400; + return 0x00000400U; } static inline u32 proj_tpc_in_gpc_base_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_tpc_in_gpc_stride_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 proj_tpc_in_gpc_shared_base_v(void) { - return 0x00001800; + return 0x00001800U; } static inline u32 proj_host_num_engines_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 proj_host_num_pbdma_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 proj_scal_litter_num_gpcs_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 proj_scal_litter_num_zcull_banks_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_max_gpcs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 proj_scal_max_tpc_per_gpc_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 proj_sm_stride_v(void) { - return 0x00000080; + return 0x00000080U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h index b85c37aa..4b0b0326 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -58,878 +58,878 @@ static inline u32 pwr_falcon_irqsset_r(void) { - return 0x0010a000; + return 0x0010a000U; } static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqsclr_r(void) { - return 0x0010a004; + return 0x0010a004U; } static inline u32 pwr_falcon_irqstat_r(void) { - return 0x0010a008; + return 0x0010a008U; } static inline u32 pwr_falcon_irqstat_halt_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 pwr_falcon_irqstat_exterr_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 pwr_falcon_irqmode_r(void) { - return 0x0010a00c; + return 0x0010a00cU; } static inline u32 pwr_falcon_irqmset_r(void) { - return 0x0010a010; + return 0x0010a010U; } static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmset_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmset_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmclr_r(void) { - return 0x0010a014; + return 0x0010a014U; } static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmask_r(void) { - return 0x0010a018; + return 0x0010a018U; } static inline u32 pwr_falcon_irqdest_r(void) { - return 0x0010a01c; + return 0x0010a01cU; } static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_falcon_curctx_r(void) { - return 0x0010a050; + return 0x0010a050U; } static inline u32 pwr_falcon_nxtctx_r(void) { - return 0x0010a054; + return 0x0010a054U; } static inline u32 pwr_falcon_mailbox0_r(void) { - return 0x0010a040; + return 0x0010a040U; } static inline u32 pwr_falcon_mailbox1_r(void) { - return 0x0010a044; + return 0x0010a044U; } static inline u32 pwr_falcon_itfen_r(void) { - return 0x0010a048; + return 0x0010a048U; } static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_falcon_idlestate_r(void) { - return 0x0010a04c; + return 0x0010a04cU; } static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) { - return (r >> 1) & 0x7fff; + return (r >> 1U) & 0x7fffU; } static inline u32 pwr_falcon_os_r(void) { - return 0x0010a080; + return 0x0010a080U; } static inline u32 pwr_falcon_engctl_r(void) { - return 0x0010a0a4; + return 0x0010a0a4U; } static inline u32 pwr_falcon_cpuctl_r(void) { - return 0x0010a100; + return 0x0010a100U; } static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_alias_r(void) { - return 0x0010a130; + return 0x0010a130U; } static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_pmu_scpctl_stat_r(void) { - return 0x0010ac08; + return 0x0010ac08U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 pwr_falcon_imemc_r(u32 i) { - return 0x0010a180 + i*16; + return 0x0010a180U + i*16U; } static inline u32 pwr_falcon_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_imemd_r(u32 i) { - return 0x0010a184 + i*16; + return 0x0010a184U + i*16U; } static inline u32 pwr_falcon_imemt_r(u32 i) { - return 0x0010a188 + i*16; + return 0x0010a188U + i*16U; } static inline u32 pwr_falcon_sctl_r(void) { - return 0x0010a240; + return 0x0010a240U; } static inline u32 pwr_falcon_mmu_phys_sec_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 pwr_falcon_bootvec_r(void) { - return 0x0010a104; + return 0x0010a104U; } static inline u32 pwr_falcon_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_falcon_dmactl_r(void) { - return 0x0010a10c; + return 0x0010a10cU; } static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_falcon_hwcfg_r(void) { - return 0x0010a108; + return 0x0010a108U; } static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) { - return (r >> 9) & 0x1ff; + return (r >> 9U) & 0x1ffU; } static inline u32 pwr_falcon_dmatrfbase_r(void) { - return 0x0010a110; + return 0x0010a110U; } static inline u32 pwr_falcon_dmatrfbase1_r(void) { - return 0x0010a128; + return 0x0010a128U; } static inline u32 pwr_falcon_dmatrfmoffs_r(void) { - return 0x0010a114; + return 0x0010a114U; } static inline u32 pwr_falcon_dmatrfcmd_r(void) { - return 0x0010a118; + return 0x0010a118U; } static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 pwr_falcon_dmatrffboffs_r(void) { - return 0x0010a11c; + return 0x0010a11cU; } static inline u32 pwr_falcon_exterraddr_r(void) { - return 0x0010a168; + return 0x0010a168U; } static inline u32 pwr_falcon_exterrstat_r(void) { - return 0x0010a16c; + return 0x0010a16cU; } static inline u32 pwr_falcon_exterrstat_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 pwr_falcon_exterrstat_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pwr_pmu_falcon_icd_cmd_r(void) { - return 0x0010a200; + return 0x0010a200U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 pwr_pmu_falcon_icd_rdata_r(void) { - return 0x0010a20c; + return 0x0010a20cU; } static inline u32 pwr_falcon_dmemc_r(u32 i) { - return 0x0010a1c0 + i*8; + return 0x0010a1c0U + i*8U; } static inline u32 pwr_falcon_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 pwr_falcon_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_dmemc_blk_m(void) { - return 0xff << 8; + return 0xffU << 8U; } static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_dmemd_r(u32 i) { - return 0x0010a1c4 + i*8; + return 0x0010a1c4U + i*8U; } static inline u32 pwr_pmu_new_instblk_r(void) { - return 0x0010a480; + return 0x0010a480U; } static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 pwr_pmu_new_instblk_target_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_pmu_mutex_id_r(void) { - return 0x0010a488; + return 0x0010a488U; } static inline u32 pwr_pmu_mutex_id_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_id_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 pwr_pmu_mutex_id_release_r(void) { - return 0x0010a48c; + return 0x0010a48cU; } static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_mutex_r(u32 i) { - return 0x0010a580 + i*4; + return 0x0010a580U + i*4U; } static inline u32 pwr_pmu_mutex__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 pwr_pmu_mutex_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_queue_head_r(u32 i) { - return 0x0010a800 + i*4; + return 0x0010a800U + i*4U; } static inline u32 pwr_pmu_queue_head__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_head_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_head_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_queue_tail_r(u32 i) { - return 0x0010a820 + i*4; + return 0x0010a820U + i*4U; } static inline u32 pwr_pmu_queue_tail__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_tail_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_tail_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_head_r(void) { - return 0x0010a4c8; + return 0x0010a4c8U; } static inline u32 pwr_pmu_msgq_head_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_head_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_tail_r(void) { - return 0x0010a4cc; + return 0x0010a4ccU; } static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_idle_mask_r(u32 i) { - return 0x0010a504 + i*16; + return 0x0010a504U + i*16U; } static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pwr_pmu_idle_count_r(u32 i) { - return 0x0010a508 + i*16; + return 0x0010a508U + i*16U; } static inline u32 pwr_pmu_idle_count_value_f(u32 v) { - return (v & 0x7fffffff) << 0; + return (v & 0x7fffffffU) << 0U; } static inline u32 pwr_pmu_idle_count_value_v(u32 r) { - return (r >> 0) & 0x7fffffff; + return (r >> 0U) & 0x7fffffffU; } static inline u32 pwr_pmu_idle_count_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 pwr_pmu_idle_ctrl_r(u32 i) { - return 0x0010a50c + i*16; + return 0x0010a50cU + i*16U; } static inline u32 pwr_pmu_idle_ctrl_value_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) { - return 0x3; + return 0x3U; } static inline u32 pwr_pmu_idle_ctrl_filter_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) { - return 0x0010a9f0 + i*8; + return 0x0010a9f0U + i*8U; } static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) { - return 0x0010a9f4 + i*8; + return 0x0010a9f4U + i*8U; } static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) { - return 0x0010aa30 + i*8; + return 0x0010aa30U + i*8U; } static inline u32 pwr_pmu_debug_r(u32 i) { - return 0x0010a5c0 + i*4; + return 0x0010a5c0U + i*4U; } static inline u32 pwr_pmu_debug__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pwr_pmu_mailbox_r(u32 i) { - return 0x0010a450 + i*4; + return 0x0010a450U + i*4U; } static inline u32 pwr_pmu_mailbox__size_1_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 pwr_pmu_bar0_addr_r(void) { - return 0x0010a7a0; + return 0x0010a7a0U; } static inline u32 pwr_pmu_bar0_data_r(void) { - return 0x0010a7a4; + return 0x0010a7a4U; } static inline u32 pwr_pmu_bar0_ctl_r(void) { - return 0x0010a7ac; + return 0x0010a7acU; } static inline u32 pwr_pmu_bar0_timeout_r(void) { - return 0x0010a7a8; + return 0x0010a7a8U; } static inline u32 pwr_pmu_bar0_fecs_error_r(void) { - return 0x0010a988; + return 0x0010a988U; } static inline u32 pwr_pmu_bar0_error_status_r(void) { - return 0x0010a7b0; + return 0x0010a7b0U; } static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) { - return 0x0010a6c0 + i*4; + return 0x0010a6c0U + i*4U; } static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) { - return 0x0010a6e8 + i*4; + return 0x0010a6e8U + i*4U; } static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) { - return 0x0010a710 + i*4; + return 0x0010a710U + i*4U; } static inline u32 pwr_pmu_pg_intren_r(u32 i) { - return 0x0010a760 + i*4; + return 0x0010a760U + i*4U; } static inline u32 pwr_fbif_transcfg_r(u32 i) { - return 0x0010ae00 + i*4; + return 0x0010ae00U + i*4U; } static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_fbif_transcfg_mem_type_s(void) { - return 1; + return 1U; } static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) { - return 0x4; + return 0x4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index 3a5bf6cb..6b3e8aa6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -58,619 +58,619 @@ static inline u32 ram_in_ramfc_s(void) { - return 4096; + return 4096U; } static inline u32 ram_in_ramfc_w(void) { - return 0; + return 0U; } static inline u32 ram_in_page_dir_base_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_page_dir_base_target_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 ram_in_page_dir_base_vol_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 ram_in_page_dir_base_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 ram_in_big_page_size_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 ram_in_big_page_size_w(void) { - return 128; + return 128U; } static inline u32 ram_in_big_page_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_big_page_size_64kb_f(void) { - return 0x800; + return 0x800U; } static inline u32 ram_in_page_dir_base_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_page_dir_base_lo_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_page_dir_base_hi_w(void) { - return 129; + return 129U; } static inline u32 ram_in_engine_cs_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_cs_wfi_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_cs_wfi_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_engine_cs_fg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_cs_fg_f(void) { - return 0x8; + return 0x8U; } static inline u32 ram_in_engine_wfi_mode_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_engine_wfi_mode_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_mode_physical_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_mode_virtual_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_wfi_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_engine_wfi_target_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_engine_wfi_target_local_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_engine_wfi_ptr_lo_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_in_engine_wfi_ptr_hi_w(void) { - return 133; + return 133U; } static inline u32 ram_in_engine_wfi_veid_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ram_in_engine_wfi_veid_w(void) { - return 134; + return 134U; } static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) { - return 136; + return 136U; } static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) { - return 137; + return 137U; } static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) { - return (v & 0x3) << (0 + i*0); + return (v & 0x3U) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) { - return (v & 0x1) << (2 + i*0); + return (v & 0x1U) << (2U + i*0U); } static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) { - return (v & 0x1) << (4 + i*0); + return (v & 0x1U) << (4U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) { - return (v & 0x1) << (5 + i*0); + return (v & 0x1U) << (5U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) { - return (v & 0x1) << (10 + i*0); + return (v & 0x1U) << (10U + i*0U); } static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) { - return (v & 0x1) << (11 + i*0); + return (v & 0x1U) << (11U + i*0U); } static inline u32 ram_in_sc_big_page_size__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_big_page_size_64kb_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) { - return (v & 0xfffff) << (12 + i*0); + return (v & 0xfffffU) << (12U + i*0U); } static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) { - return (v & 0xffffffff) << (0 + i*0); + return (v & 0xffffffffU) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_sc_page_dir_base_target_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_big_page_size_0_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_sc_big_page_size_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) { - return 169; + return 169U; } static inline u32 ram_in_base_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ram_in_alloc_size_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ram_fc_size_val_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_fc_gp_put_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_userd_w(void) { - return 2; + return 2U; } static inline u32 ram_fc_userd_hi_w(void) { - return 3; + return 3U; } static inline u32 ram_fc_signature_w(void) { - return 4; + return 4U; } static inline u32 ram_fc_gp_get_w(void) { - return 5; + return 5U; } static inline u32 ram_fc_pb_get_w(void) { - return 6; + return 6U; } static inline u32 ram_fc_pb_get_hi_w(void) { - return 7; + return 7U; } static inline u32 ram_fc_pb_top_level_get_w(void) { - return 8; + return 8U; } static inline u32 ram_fc_pb_top_level_get_hi_w(void) { - return 9; + return 9U; } static inline u32 ram_fc_acquire_w(void) { - return 12; + return 12U; } static inline u32 ram_fc_sem_addr_hi_w(void) { - return 14; + return 14U; } static inline u32 ram_fc_sem_addr_lo_w(void) { - return 15; + return 15U; } static inline u32 ram_fc_sem_payload_lo_w(void) { - return 16; + return 16U; } static inline u32 ram_fc_sem_payload_hi_w(void) { - return 39; + return 39U; } static inline u32 ram_fc_sem_execute_w(void) { - return 17; + return 17U; } static inline u32 ram_fc_gp_base_w(void) { - return 18; + return 18U; } static inline u32 ram_fc_gp_base_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_fc_gp_fetch_w(void) { - return 20; + return 20U; } static inline u32 ram_fc_pb_fetch_w(void) { - return 21; + return 21U; } static inline u32 ram_fc_pb_fetch_hi_w(void) { - return 22; + return 22U; } static inline u32 ram_fc_pb_put_w(void) { - return 23; + return 23U; } static inline u32 ram_fc_pb_put_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_fc_pb_header_w(void) { - return 33; + return 33U; } static inline u32 ram_fc_pb_count_w(void) { - return 34; + return 34U; } static inline u32 ram_fc_subdevice_w(void) { - return 37; + return 37U; } static inline u32 ram_fc_target_w(void) { - return 43; + return 43U; } static inline u32 ram_fc_hce_ctrl_w(void) { - return 57; + return 57U; } static inline u32 ram_fc_chid_w(void) { - return 58; + return 58U; } static inline u32 ram_fc_chid_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_fc_chid_id_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_config_w(void) { - return 61; + return 61U; } static inline u32 ram_fc_runlist_timeslice_w(void) { - return 62; + return 62U; } static inline u32 ram_fc_set_channel_info_w(void) { - return 63; + return 63U; } static inline u32 ram_userd_base_shift_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 ram_userd_chan_size_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_userd_put_w(void) { - return 16; + return 16U; } static inline u32 ram_userd_get_w(void) { - return 17; + return 17U; } static inline u32 ram_userd_ref_w(void) { - return 18; + return 18U; } static inline u32 ram_userd_put_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_userd_ref_threshold_w(void) { - return 20; + return 20U; } static inline u32 ram_userd_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_userd_get_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_userd_gp_get_w(void) { - return 34; + return 34U; } static inline u32 ram_userd_gp_put_w(void) { - return 35; + return 35U; } static inline u32 ram_userd_gp_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_gp_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_rl_entry_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ram_rl_entry_type_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 ram_rl_entry_type_channel_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_type_tsg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) { - return (v & 0x3) << 4; + return (v & 0x3U) << 4U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) { @@ -682,94 +682,94 @@ static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) } static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { - return (v & 0x3) << 6; + return (v & 0x3U) << 6U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_rl_entry_tsg_length_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_min_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_tsg_length_max_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h index 2834acf8..2ea71ef1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -58,242 +58,242 @@ static inline u32 therm_weight_1_r(void) { - return 0x00020024; + return 0x00020024U; } static inline u32 therm_config1_r(void) { - return 0x00020050; + return 0x00020050U; } static inline u32 therm_config2_r(void) { - return 0x00020130; + return 0x00020130U; } static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 therm_config2_grad_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 therm_gate_ctrl_r(u32 i) { - return 0x00020200 + i*4; + return 0x00020200U + i*4U; } static inline u32 therm_gate_ctrl_eng_clk_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 therm_gate_ctrl_eng_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_gate_ctrl_blk_clk_m(void) { - return 0x3 << 2; + return 0x3U << 2U; } static inline u32 therm_gate_ctrl_blk_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) { - return 0x4; + return 0x4U; } static inline u32 therm_gate_ctrl_idle_holdoff_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) { - return 0x10; + return 0x10U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { - return 0x1f << 8; + return 0x1fU << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { - return (v & 0x7) << 13; + return (v & 0x7U) << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { - return 0x7 << 13; + return 0x7U << 13U; } static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { - return 0xf << 16; + return 0xfU << 16U; } static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { - return 0xf << 20; + return 0xfU << 20U; } static inline u32 therm_fecs_idle_filter_r(void) { - return 0x00020288; + return 0x00020288U; } static inline u32 therm_fecs_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_hubmmu_idle_filter_r(void) { - return 0x0002028c; + return 0x0002028cU; } static inline u32 therm_hubmmu_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_clk_slowdown_r(u32 i) { - return 0x00020160 + i*4; + return 0x00020160U + i*4U; } static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) { - return (v & 0x3f) << 16; + return (v & 0x3fU) << 16U; } static inline u32 therm_clk_slowdown_idle_factor_m(void) { - return 0x3f << 16; + return 0x3fU << 16U; } static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) { - return (r >> 16) & 0x3f; + return (r >> 16U) & 0x3fU; } static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_grad_stepping_table_r(u32 i) { - return 0x000202c8 + i*4; + return 0x000202c8U + i*4U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) { - return 0x6; + return 0x6U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) { - return 0xe; + return 0xeU; } static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) { - return (v & 0x3f) << 12; + return (v & 0x3fU) << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) { - return 0x3f << 12; + return 0x3fU << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) { - return (v & 0x3f) << 18; + return (v & 0x3fU) << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) { - return 0x3f << 18; + return 0x3fU << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) { - return 0x3f << 24; + return 0x3fU << 24U; } static inline u32 therm_grad_stepping0_r(void) { - return 0x000202c0; + return 0x000202c0U; } static inline u32 therm_grad_stepping0_feature_s(void) { - return 1; + return 1U; } static inline u32 therm_grad_stepping0_feature_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 therm_grad_stepping0_feature_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 therm_grad_stepping0_feature_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 therm_grad_stepping0_feature_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping1_r(void) { - return 0x000202c4; + return 0x000202c4U; } static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 therm_clk_timing_r(u32 i) { - return 0x000203c0 + i*4; + return 0x000203c0U + i*4U; } static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 therm_clk_timing_grad_slowdown_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h index d53deb15..9d76e241 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -58,58 +58,58 @@ static inline u32 timer_pri_timeout_r(void) { - return 0x00009080; + return 0x00009080U; } static inline u32 timer_pri_timeout_period_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 timer_pri_timeout_period_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 timer_pri_timeout_period_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 timer_pri_timeout_en_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 timer_pri_timeout_en_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 timer_pri_timeout_en_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 timer_pri_timeout_en_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 timer_pri_timeout_en_en_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 timer_pri_timeout_save_0_r(void) { - return 0x00009084; + return 0x00009084U; } static inline u32 timer_pri_timeout_save_1_r(void) { - return 0x00009088; + return 0x00009088U; } static inline u32 timer_pri_timeout_fecs_errcode_r(void) { - return 0x0000908c; + return 0x0000908cU; } static inline u32 timer_time_0_r(void) { - return 0x00009400; + return 0x00009400U; } static inline u32 timer_time_1_r(void) { - return 0x00009410; + return 0x00009410U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index 35b3ab33..da297b72 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -58,178 +58,178 @@ static inline u32 top_num_gpcs_r(void) { - return 0x00022430; + return 0x00022430U; } static inline u32 top_num_gpcs_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_tpc_per_gpc_r(void) { - return 0x00022434; + return 0x00022434U; } static inline u32 top_tpc_per_gpc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_fbps_r(void) { - return 0x00022438; + return 0x00022438U; } static inline u32 top_num_fbps_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_ltc_per_fbp_r(void) { - return 0x00022450; + return 0x00022450U; } static inline u32 top_ltc_per_fbp_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_slices_per_ltc_r(void) { - return 0x0002245c; + return 0x0002245cU; } static inline u32 top_slices_per_ltc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_ltcs_r(void) { - return 0x00022454; + return 0x00022454U; } static inline u32 top_num_ces_r(void) { - return 0x00022444; + return 0x00022444U; } static inline u32 top_num_ces_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_device_info_r(u32 i) { - return 0x00022700 + i*4; + return 0x00022700U + i*4U; } static inline u32 top_device_info__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 top_device_info_chain_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 top_device_info_chain_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_engine_enum_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_runlist_enum_v(u32 r) { - return (r >> 21) & 0xf; + return (r >> 21U) & 0xfU; } static inline u32 top_device_info_intr_enum_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 top_device_info_reset_enum_v(u32 r) { - return (r >> 9) & 0x1f; + return (r >> 9U) & 0x1fU; } static inline u32 top_device_info_type_enum_v(u32 r) { - return (r >> 2) & 0x1fffffff; + return (r >> 2U) & 0x1fffffffU; } static inline u32 top_device_info_type_enum_graphics_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_type_enum_graphics_f(void) { - return 0x0; + return 0x0U; } static inline u32 top_device_info_type_enum_copy2_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 top_device_info_type_enum_copy2_f(void) { - return 0xc; + return 0xcU; } static inline u32 top_device_info_type_enum_lce_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 top_device_info_type_enum_lce_f(void) { - return 0x4c; + return 0x4cU; } static inline u32 top_device_info_engine_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 top_device_info_runlist_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 top_device_info_intr_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 top_device_info_reset_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_entry_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 top_device_info_entry_not_valid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_entry_enum_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 top_device_info_entry_data_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_data_type_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 top_device_info_data_type_enum2_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_data_inst_id_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_data_pri_base_v(u32 r) { - return (r >> 12) & 0xfff; + return (r >> 12U) & 0xfffU; } static inline u32 top_device_info_data_pri_base_align_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 top_device_info_data_fault_id_enum_v(u32 r) { - return (r >> 3) & 0x7f; + return (r >> 3U) & 0x7fU; } static inline u32 top_device_info_data_fault_id_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_data_fault_id_valid_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h index d49c9eed..7b1d861e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -58,38 +58,38 @@ static inline u32 usermode_cfg0_r(void) { - return 0x00810000; + return 0x00810000U; } static inline u32 usermode_cfg0_class_id_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 usermode_cfg0_class_id_value_v(void) { - return 0x0000c361; + return 0x0000c361U; } static inline u32 usermode_time_0_r(void) { - return 0x00810080; + return 0x00810080U; } static inline u32 usermode_time_0_nsec_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 usermode_time_1_r(void) { - return 0x00810084; + return 0x00810084U; } static inline u32 usermode_time_1_nsec_f(u32 v) { - return (v & 0x1fffffff) << 0; + return (v & 0x1fffffffU) << 0U; } static inline u32 usermode_notify_channel_pending_r(void) { - return 0x00810090; + return 0x00810090U; } static inline u32 usermode_notify_channel_pending_id_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h index 8680c11a..4296e043 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -58,86 +58,86 @@ static inline u32 xp_dl_mgr_r(u32 i) { - return 0x0008b8c0 + i*4; + return 0x0008b8c0U + i*4U; } static inline u32 xp_dl_mgr_safe_timing_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 xp_pl_link_config_r(u32 i) { - return 0x0008c040 + i*4; + return 0x0008c040U + i*4U; } static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 xp_pl_link_config_ltssm_directive_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) { - return (v & 0x3) << 18; + return (v & 0x3U) << 18U; } static inline u32 xp_pl_link_config_max_link_rate_m(void) { - return 0x3 << 18; + return 0x3U << 18U; } static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x7U) << 20U; } static inline u32 xp_pl_link_config_target_tx_width_m(void) { - return 0x7 << 20; + return 0x7U << 20U; } static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) { - return 0x00000000; + return 0x00000000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h index 534f66b3..fc7aa72e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -58,150 +58,150 @@ static inline u32 xve_rom_ctrl_r(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 xve_link_control_status_r(void) { - return 0x00000088; + return 0x00000088U; } static inline u32 xve_link_control_status_link_speed_m(void) { - return 0xf << 16; + return 0xfU << 16U; } static inline u32 xve_link_control_status_link_speed_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 xve_link_control_status_link_width_m(void) { - return 0x3f << 20; + return 0x3fU << 20U; } static inline u32 xve_link_control_status_link_width_v(u32 r) { - return (r >> 20) & 0x3f; + return (r >> 20U) & 0x3fU; } static inline u32 xve_link_control_status_link_width_x1_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xve_link_control_status_link_width_x2_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 xve_link_control_status_link_width_x4_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 xve_link_control_status_link_width_x8_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 xve_link_control_status_link_width_x16_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 xve_priv_xv_r(void) { - return 0x00000150; + return 0x00000150U; } static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 xve_priv_xv_cya_l0s_enable_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 xve_priv_xv_cya_l1_enable_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 xve_cya_2_r(void) { - return 0x00000704; + return 0x00000704U; } static inline u32 xve_reset_r(void) { - return 0x00000718; + return 0x00000718U; } static inline u32 xve_reset_reset_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 xve_reset_gpu_on_sw_reset_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 xve_reset_counter_en_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 xve_reset_counter_val_f(u32 v) { - return (v & 0x7ff) << 4; + return (v & 0x7ffU) << 4U; } static inline u32 xve_reset_counter_val_m(void) { - return 0x7ff << 4; + return 0x7ffU << 4U; } static inline u32 xve_reset_counter_val_v(u32 r) { - return (r >> 4) & 0x7ff; + return (r >> 4U) & 0x7ffU; } static inline u32 xve_reset_clock_on_sw_reset_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 xve_reset_clock_counter_en_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 xve_reset_clock_counter_val_f(u32 v) { - return (v & 0x7ff) << 17; + return (v & 0x7ffU) << 17U; } static inline u32 xve_reset_clock_counter_val_m(void) { - return 0x7ff << 17; + return 0x7ffU << 17U; } static inline u32 xve_reset_clock_counter_val_v(u32 r) { - return (r >> 17) & 0x7ff; + return (r >> 17U) & 0x7ffU; } #endif -- cgit v1.2.2 From b0092ea95c6e1f695912cdb0b13767f3881cb22f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Sep 2017 15:05:50 -0700 Subject: gpu: nvgpu: gv11b: Abstract IO aperture accessors Implement T19x specific usermode aperture initialization functions. Move usermode_regs field to nvgpu_os_linux_t19x, because it is Linux specific. JIRA NVGPU-259 Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1569699 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/io_t19x.h | 29 ++++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h | 26 +++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/linux/module_t19x.h | 27 ++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h | 26 +++++++++++++++++++ 4 files changed, 108 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/io_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h new file mode 100644 index 00000000..f8c7dbbd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVGPU_IO_T19X_H__ +#define __NVGPU_IO_T19X_H__ + +#ifdef __KERNEL__ +#include "linux/io_t19x.h" +#endif + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h new file mode 100644 index 00000000..f71a6ecf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_IO_T19X_LINUX_H__ +#define __NVGPU_IO_T19X_LINUX_H__ + +#include + +struct gk20a; + +void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h new file mode 100644 index 00000000..a105c6dc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_MODULE_T19X_H__ +#define __NVGPU_MODULE_T19X_H__ + +struct gk20a; + +void t19x_init_support(struct gk20a *g); +void t19x_remove_support(struct gk20a *g); +void t19x_lockout_registers(struct gk20a *g); +void t19x_restore_registers(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h new file mode 100644 index 00000000..a306bfb8 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef NVGPU_OS_LINUX_T19X_H +#define NVGPU_OS_LINUX_T19X_H + +#include + +struct nvgpu_os_linux_t19x { + void __iomem *usermode_regs; + void __iomem *usermode_regs_saved; +}; + +#endif -- cgit v1.2.2 From 7612e412151c676c4e7af08839bd98d879a25dea Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 2 Oct 2017 16:37:50 -0700 Subject: gpu: nvgpu: gvxx: add hw defines for pbdma info Generated following hw definitions to dump relevant data: pbdma_gp_shadow_0_r pbdma_gp_shadow_1_r Bug 2003671 Change-Id: If2d0557b3c2896747793ff2afad875206e25c6d8 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1572183 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 8 ++++++++ 2 files changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index 2d98b914..66a0737c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -172,6 +172,14 @@ static inline u32 pbdma_hdr_shadow_r(u32 i) { return 0x00040118U + i*8192U; } +static inline u32 pbdma_gp_shadow_0_r(u32 i) +{ + return 0x00040110U + i*8192U; +} +static inline u32 pbdma_gp_shadow_1_r(u32 i) +{ + return 0x00040114U + i*8192U; +} static inline u32 pbdma_subdevice_r(u32 i) { return 0x00040094U + i*8192U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 74ff4002..9b9017ee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -172,6 +172,14 @@ static inline u32 pbdma_hdr_shadow_r(u32 i) { return 0x00040118U + i*8192U; } +static inline u32 pbdma_gp_shadow_0_r(u32 i) +{ + return 0x00040110U + i*8192U; +} +static inline u32 pbdma_gp_shadow_1_r(u32 i) +{ + return 0x00040114U + i*8192U; +} static inline u32 pbdma_subdevice_r(u32 i) { return 0x00040094U + i*8192U; -- cgit v1.2.2 From 0c40a3e034cd9450859dfe713c4d1ca134b77b7e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sat, 14 Oct 2017 07:53:06 -0700 Subject: gpu: nvgpu: Initialize usermode regs for Volta dGPU Initialize usermode registers also for Volta GPU behind PCIe. Change-Id: Id621a74838839e4d98dfd0828c1ea5a0d54baa2d Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1579121 Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h new file mode 100644 index 00000000..c94176cc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __NVGPU_PCI_T19X_H__ +#define __NVGPU_PCI_T19X_H__ + +struct nvgpu_os_linux; + +void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l); + +#endif -- cgit v1.2.2 From e78cd6c42aec3ae18f12420fd8eb4cb58d09da2d Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 12 Oct 2017 11:35:32 -0700 Subject: gpu: nvgpu: add missing hal defines Due to lack of GVS coverage some defines were left out in GV100, this change adds them back JIRA: NVGPUGV100-9 Change-Id: I2f5778529dcad535bb56c33c38c097415dbf11e5 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1577998 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel --- .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index 52a7dfc4..dc4c377d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -76,6 +76,14 @@ static inline u32 proj_lts_stride_v(void) { return 0x00000200U; } +static inline u32 proj_fbpa_base_v(void) +{ + return 0x00900000U; +} +static inline u32 proj_fbpa_shared_base_v(void) +{ + return 0x009a0000U; +} static inline u32 proj_fbpa_stride_v(void) { return 0x00004000U; @@ -84,6 +92,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) { return 0x00003000U; } +static inline u32 proj_ppc_in_gpc_shared_base_v(void) +{ + return 0x00003e00U; +} static inline u32 proj_ppc_in_gpc_stride_v(void) { return 0x00000200U; @@ -112,6 +124,22 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) { return 0x00001800U; } +static inline u32 proj_smpc_base_v(void) +{ + return 0x00000200U; +} +static inline u32 proj_smpc_shared_base_v(void) +{ + return 0x00000300U; +} +static inline u32 proj_smpc_unique_base_v(void) +{ + return 0x00000600U; +} +static inline u32 proj_smpc_stride_v(void) +{ + return 0x00000100U; +} static inline u32 proj_host_num_engines_v(void) { return 0x0000000fU; -- cgit v1.2.2 From 2904e3ac0081d4e898378f6ba667658c85547368 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 4 Oct 2017 19:41:04 +0530 Subject: gpu: nvgpu: gv100 memory unlock support - Added method to load mem unlock binary into nvdec falcon & execute to perform mem unlock if VPR enabled. - Updated .mem_unlock gv100 HAL to point method gv100_fb_memory_unlock(). - Updated .mem_unlock gv11b HAL to NULL. - Added vpr info hw registers - Added nvdec enable hw register Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a Signed-off-by: Mahantesh Kumbar (cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb) Reviewed-on: https://git-master.nvidia.com/r/1573101 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 36 ++++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 8 +++++ 2 files changed, 44 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index 3bba3fb8..a4fcd1e6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -460,6 +460,42 @@ static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0U; } +static inline u32 fb_mmu_vpr_info_index_f(u32 v) +{ + return (v & 0x3U) << 0U; +} +static inline u32 fb_mmu_vpr_info_index_v(u32 r) +{ + return (r >> 0U) & 0x3U; +} +static inline u32 fb_mmu_vpr_info_index_m(void) +{ + return 0x3U << 0U; +} +static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) +{ + return 0x00000000U; +} +static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) +{ + return 0x00000001U; +} +static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) +{ + return 0x00000002U; +} +static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) +{ + return 0x00000003U; +} +static inline u32 fb_mmu_vpr_info_cya_lo_in_use_m(void) +{ + return 0x1U << 4U; +} +static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) +{ + return (v & 0x1U) << 2U; +} static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { return (r >> 2U) & 0x1U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 2efeac79..f367991e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -196,6 +196,14 @@ static inline u32 mc_enable_hub_enabled_f(void) { return 0x20000000U; } +static inline u32 mc_enable_nvdec_disabled_v(void) +{ + return 0x00000000U; +} +static inline u32 mc_enable_nvdec_enabled_f(void) +{ + return 0x8000U; +} static inline u32 mc_intr_ltc_r(void) { return 0x000001c0U; -- cgit v1.2.2 From 1b6669957330312f0336bc207a64668782129048 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Oct 2017 14:49:01 -0700 Subject: gpu: nvgpu: gvxx: enhance class error debug info Generated following hw definitions for gv100 and gv11b to dump relevant data in gk20a_gr_handle_class_error: gr_trapped_addr_mme_generated_v gr_trapped_addr_datahigh_v gr_trapped_addr_priv_v gr_trapped_data_lo_r gr_trapped_data_mme_r gr_trapped_data_mme_pc_v Bug 2003671 Change-Id: I055c693458625e1cdbbcdaa63ee4b0efd3697015 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1582848 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 24 ++++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 24 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index bdd749d0..09cbc793 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -284,6 +284,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r) { return (r >> 16U) & 0x7U; } +static inline u32 gr_trapped_addr_mme_generated_v(u32 r) +{ + return (r >> 20U) & 0x1U; +} +static inline u32 gr_trapped_addr_datahigh_v(u32 r) +{ + return (r >> 24U) & 0x1U; +} +static inline u32 gr_trapped_addr_priv_v(u32 r) +{ + return (r >> 28U) & 0x1U; +} +static inline u32 gr_trapped_addr_status_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} static inline u32 gr_trapped_data_lo_r(void) { return 0x00400708U; @@ -292,6 +308,14 @@ static inline u32 gr_trapped_data_hi_r(void) { return 0x0040070cU; } +static inline u32 gr_trapped_data_mme_r(void) +{ + return 0x00400710U; +} +static inline u32 gr_trapped_data_mme_pc_v(u32 r) +{ + return (r >> 0U) & 0xfffU; +} static inline u32 gr_status_r(void) { return 0x00400700U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 3bdf2de2..692b7ba3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -284,6 +284,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r) { return (r >> 16U) & 0x7U; } +static inline u32 gr_trapped_addr_mme_generated_v(u32 r) +{ + return (r >> 20U) & 0x1U; +} +static inline u32 gr_trapped_addr_datahigh_v(u32 r) +{ + return (r >> 24U) & 0x1U; +} +static inline u32 gr_trapped_addr_priv_v(u32 r) +{ + return (r >> 28U) & 0x1U; +} +static inline u32 gr_trapped_addr_status_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} static inline u32 gr_trapped_data_lo_r(void) { return 0x00400708U; @@ -292,6 +308,14 @@ static inline u32 gr_trapped_data_hi_r(void) { return 0x0040070cU; } +static inline u32 gr_trapped_data_mme_r(void) +{ + return 0x00400710U; +} +static inline u32 gr_trapped_data_mme_pc_v(u32 r) +{ + return (r >> 0U) & 0xfffU; +} static inline u32 gr_status_r(void) { return 0x00400700U; -- cgit v1.2.2 From 0956d26143b5313f590fcaf008a2182a08b9967c Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Oct 2017 14:52:43 -0700 Subject: gpu: nvgpu: gv11b: sync hw header defines with generator Updated hw_therm_gv11b related defines to sync with tool generated output. Change-Id: I9c6e879636730eda1c4608d6e18f47c3fe55893e Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1582849 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index ce265901..8f8981e8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -242,7 +242,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) } static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) { - return 0x200; + return 0x200U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { @@ -254,7 +254,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) } static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { @@ -266,7 +266,7 @@ static inline u32 therm_gate_ctrl_eng_delay_before_m(void) } static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { @@ -278,7 +278,7 @@ static inline u32 therm_gate_ctrl_eng_delay_after_m(void) } static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_fecs_idle_filter_r(void) { @@ -290,7 +290,7 @@ static inline u32 therm_fecs_idle_filter_value_m(void) } static inline u32 therm_fecs_idle_filter_value__prod_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_hubmmu_idle_filter_r(void) { @@ -302,7 +302,7 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) } static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_clk_slowdown_r(u32 i) { -- cgit v1.2.2 From 938785f1525ce0ae654c2be0911e15816617995d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 23 Oct 2017 08:45:13 -0700 Subject: gpu: nvgpu: Linux specific GPU characteristics flags Make GPU characteristics flags specific to Linux code only. The rest of driver is moved to using nvgpu_is_enabled() API. JIRA NVGPU-259 Change-Id: I46a5a90bb34f170e9e755e7683be142ed6b18cce Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1583992 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h new file mode 100644 index 00000000..9ef1dc30 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_ENABLED_T19X_H__ +#define __NVGPU_ENABLED_T19X_H__ + +/* subcontexts are available */ +#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 + +#endif -- cgit v1.2.2 From 4f24e212cbd66a58cbae9fdf810694d01f57ee5f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 22 Sep 2017 11:10:11 -0700 Subject: gpu: nvgpu: gv11b: replay invalid pte faults only Try to fix invalid pte type repalayable faults only. All other replayable faults will be cancelled so that next mmu fault for same fault address will be triggered as non-replayable fault and ch/tsg teardown will take place. Bug 1958308 Change-Id: I63b90ce7c639ee183f87db3e771f253fd04c3567 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1566576 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index c39cc2d8..0a442b1f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1272,6 +1272,10 @@ static inline u32 gmmu_fault_type_unbound_inst_block_v(void) { return 0x00000004U; } +static inline u32 gmmu_fault_type_pte_v(void) +{ + return 0x00000002U; +} static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) { return 0x00000005U; -- cgit v1.2.2