From ae809fddbe90bcec0d48e1213fa36cc5ba76550d Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Tue, 28 Aug 2018 11:58:25 +0530 Subject: gpu:nvgpu: Add GV10x perf event In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 5f875707..e2a0cbf7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -878,7 +878,6 @@ struct gpu_ops { u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g, struct nv_pmu_clk_rpc *rpccall, struct set_fll_clk *setfllclk); - u32 (*perf_pmu_vfe_load)(struct gk20a *g); u32 (*clk_set_boot_clk)(struct gk20a *g); }clk; } pmu_ver; @@ -1113,6 +1112,7 @@ struct gpu_ops { bool support_clk_freq_controller; bool support_pmgr_domain; bool support_lpwr_pg; + u32 (*perf_pmu_vfe_load)(struct gk20a *g); } clk; struct { int (*arbiter_clk_init)(struct gk20a *g); -- cgit v1.2.2