From 98186ec2c2127c2af65a34f9e697e04f518a79ab Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Thu, 3 Aug 2017 15:34:44 +0530 Subject: gpu: nvgpu: Add wrapper over atomic_t and atomic64_t - added wrapper structs nvgpu_atomic_t and nvgpu_atomic64_t over atomic_t and atomic64_t - added nvgpu_atomic_* and nvgpu_atomic64_* APIs to access the above wrappers. JIRA NVGPU-121 Change-Id: I61667bb0a84c2fc475365abb79bffb42b8b4786a Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1533044 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/nvgpu/atomic.h | 98 +++++++++++++++++- drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h | 137 +++++++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 12 +-- 3 files changed, 237 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/atomic.h index 700e29fe..c7a5fcd9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/atomic.h +++ b/drivers/gpu/nvgpu/include/nvgpu/atomic.h @@ -9,12 +9,102 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ #ifndef __NVGPU_ATOMIC_H__ #define __NVGPU_ATOMIC_H__ -#ifdef __KERNEL__ -#include -#endif +#include + +#define NVGPU_ATOMIC_INIT(i) __nvgpu_atomic_init(i) +#define NVGPU_ATOMIC64_INIT(i) __nvgpu_atomic64_init(i) + +static inline void nvgpu_atomic_set(nvgpu_atomic_t *v, int i) +{ + __nvgpu_atomic_set(v, i); +} +static inline int nvgpu_atomic_read(nvgpu_atomic_t *v) +{ + return __nvgpu_atomic_read(v); +} +static inline void nvgpu_atomic_inc(nvgpu_atomic_t *v) +{ + __nvgpu_atomic_inc(v); +} +static inline int nvgpu_atomic_inc_return(nvgpu_atomic_t *v) +{ + return __nvgpu_atomic_inc_return(v); +} +static inline void nvgpu_atomic_dec(nvgpu_atomic_t *v) +{ + __nvgpu_atomic_dec(v); +} +static inline int nvgpu_atomic_dec_return(nvgpu_atomic_t *v) +{ + return __nvgpu_atomic_dec_return(v); +} +static inline int nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) +{ + return __nvgpu_atomic_cmpxchg(v, old, new); +} +static inline int nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) +{ + return __nvgpu_atomic_xchg(v, new); +} +static inline bool nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) +{ + return __nvgpu_atomic_inc_and_test(v); +} +static inline bool nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) +{ + return __nvgpu_atomic_dec_and_test(v); +} +static inline int nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) +{ + return __nvgpu_atomic_add_return(i, v); +} +static inline void nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) +{ + return __nvgpu_atomic64_set(v, i); +} +static inline long nvgpu_atomic64_read(nvgpu_atomic64_t *v) +{ + return __nvgpu_atomic64_read(v); +} +static inline void nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) +{ + __nvgpu_atomic64_add(x, v); +} +static inline void nvgpu_atomic64_inc(nvgpu_atomic64_t *v) +{ + __nvgpu_atomic64_inc(v); +} +static inline long nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) +{ + return __nvgpu_atomic64_inc_return(v); +} +static inline void nvgpu_atomic64_dec(nvgpu_atomic64_t *v) +{ + __nvgpu_atomic64_dec(v); +} +static inline void nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) +{ + __nvgpu_atomic64_dec_return(v); +} +static inline long nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, long old, + long new) +{ + return __nvgpu_atomic64_cmpxchg(v, old, new); +} +static inline void nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) +{ + __nvgpu_atomic64_sub(x, v); +} +static inline long nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) +{ + return __nvgpu_atomic64_sub_return(x, v); +} -#endif +#endif /* __NVGPU_ATOMIC_H__ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h new file mode 100644 index 00000000..c6dd4650 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __NVGPU_ATOMIC_LINUX_H__ +#define __NVGPU_ATOMIC_LINUX_H__ + +#include + +typedef struct nvgpu_atomic { + atomic_t atomic_var; +} nvgpu_atomic_t; + +typedef struct nvgpu_atomic64 { + atomic64_t atomic_var; +} nvgpu_atomic64_t; + +#define __nvgpu_atomic_init(i) { ATOMIC_INIT(i) } +#define __nvgpu_atomic64_init(i) { ATOMIC64_INIT(i) } + +static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i) +{ + atomic_set(&v->atomic_var, i); +} + +static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v) +{ + return atomic_read(&v->atomic_var); +} + +static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v) +{ + atomic_inc(&v->atomic_var); +} + +static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v) +{ + return atomic_inc_return(&v->atomic_var); +} + +static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v) +{ + atomic_dec(&v->atomic_var); +} + +static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v) +{ + return atomic_dec_return(&v->atomic_var); +} + +static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) +{ + return atomic_cmpxchg(&v->atomic_var, old, new); +} + +static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) +{ + return atomic_xchg(&v->atomic_var, new); +} + +static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) +{ + return atomic_inc_and_test(&v->atomic_var); +} + +static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) +{ + return atomic_dec_and_test(&v->atomic_var); +} + +static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) +{ + return atomic_add_return(i, &v->atomic_var); +} + +static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) +{ + atomic64_set(&v->atomic_var, i); +} + +static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v) +{ + return atomic64_read(&v->atomic_var); +} + +static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) +{ + atomic64_add(x, &v->atomic_var); +} + +static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v) +{ + atomic64_inc(&v->atomic_var); +} + +static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) +{ + return atomic64_inc_return(&v->atomic_var); +} + +static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v) +{ + atomic64_dec(&v->atomic_var); +} + +static inline void __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) +{ + atomic64_dec_return(&v->atomic_var); +} + +static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, + long old, long new) +{ + return atomic64_cmpxchg(&v->atomic_var, old, new); +} + +static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) +{ + atomic64_sub(x, &v->atomic_var); +} + +static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) +{ + return atomic64_sub_return(x, &v->atomic_var); +} +#endif /*__NVGPU_ATOMIC_LINUX_H__ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index faa8d945..90261d81 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h @@ -48,7 +48,7 @@ struct nvgpu_semaphore_sea; struct nvgpu_semaphore_int { int idx; /* Semaphore index. */ u32 offset; /* Offset into the pool. */ - atomic_t next_value; /* Next available value. */ + nvgpu_atomic_t next_value; /* Next available value. */ u32 nr_incrs; /* Number of increments programmed. */ struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */ struct channel_gk20a *ch; /* Channel that owns this sema. */ @@ -70,7 +70,7 @@ nvgpu_semaphore_int_from_hw_sema_list(struct nvgpu_list_node *node) struct nvgpu_semaphore { struct nvgpu_semaphore_int *hw_sema; - atomic_t value; + nvgpu_atomic_t value; int incremented; struct kref ref; @@ -242,7 +242,7 @@ static inline bool nvgpu_semaphore_is_released(struct nvgpu_semaphore *s) * the value of the semaphore then the semaphore has been signaled * (a.k.a. released). */ - return (int)sema_val >= atomic_read(&s->value); + return (int)sema_val >= nvgpu_atomic_read(&s->value); } static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) @@ -252,12 +252,12 @@ static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) static inline u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s) { - return (u32)atomic_read(&s->value); + return (u32)nvgpu_atomic_read(&s->value); } static inline u32 nvgpu_semaphore_next_value(struct nvgpu_semaphore *s) { - return (u32)atomic_read(&s->hw_sema->next_value); + return (u32)nvgpu_atomic_read(&s->hw_sema->next_value); } /* @@ -320,7 +320,7 @@ static inline void nvgpu_semaphore_incr(struct nvgpu_semaphore *s) { BUG_ON(s->incremented); - atomic_set(&s->value, atomic_add_return(1, &s->hw_sema->next_value)); + nvgpu_atomic_set(&s->value, nvgpu_atomic_add_return(1, &s->hw_sema->next_value)); s->incremented = 1; gpu_sema_verbose_dbg(s->hw_sema->p->sema_sea->gk20a, -- cgit v1.2.2