From 8c246cb18df28bac83297df2c9d0c47725b94273 Mon Sep 17 00:00:00 2001
From: David Nieto <dmartineznie@nvidia.com>
Date: Fri, 5 May 2017 14:22:06 -0700
Subject: gpu: nvgpu: gv11b: MMU parity HWW error intr

Adding support for ISR handling of ecc uncorrectable errors
for volta resiliency (Volta-686)

TODO: move interrupt init out of MC

bug 1881052
JIRA: GPUT19X-82

Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1476603
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)

(limited to 'drivers/gpu/nvgpu/include')

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
index 45cb0ad5..76b4e902 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
@@ -462,6 +462,42 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
 {
 	return 0x00000001;
 }
+static inline u32 fb_mmu_l2tlb_ecc_status_r(void)
+{
+	return 0x00100e70;
+}
+static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 fb_mmu_hubtlb_ecc_status_r(void)
+{
+	return 0x00100e84;
+}
+static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 fb_mmu_fillunit_ecc_status_r(void)
+{
+	return 0x00100e98;
+}
+static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void)
+{
+	return 0x40000000;
+}
 static inline u32 fb_niso_flush_sysmem_addr_r(void)
 {
 	return 0x00100c10;
@@ -526,6 +562,14 @@ static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_f(u32 v)
+{
+	return (v & 0x1) << 26;
+}
+static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void)
+{
+	return 0x4000000;
+}
 static inline u32 fb_niso_intr_en_r(u32 i)
 {
 	return 0x00100a24 + i*4;
@@ -590,6 +634,14 @@ static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v)
+{
+	return (v & 0x1) << 26;
+}
+static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void)
+{
+	return 0x4000000;
+}
 static inline u32 fb_niso_intr_en_set_r(u32 i)
 {
 	return 0x00100a2c + i*4;
@@ -654,6 +706,14 @@ static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_f(u32 v)
+{
+	return (v & 0x1) << 26;
+}
+static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void)
+{
+	return 0x4000000;
+}
 static inline u32 fb_niso_intr_en_clr_r(u32 i)
 {
 	return 0x00100a34 + i*4;
@@ -718,6 +778,14 @@ static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_f(u32 v)
+{
+	return (v & 0x1) << 26;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void)
+{
+	return 0x4000000;
+}
 static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void)
 {
 	return 0x00000000;
-- 
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