From 8a1d51fe49da0d2351ee5ece472c8cdf399f0f6a Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 19 Feb 2018 12:10:37 +0530 Subject: gpu: nvgpu: gv10x volt policy boardobj changes - Added support for single rail multi step volt policy & below are the list of define & struct added/updated to support same. CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04, NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04, Updated struct vbios_voltage_policy_table_1x_entry, struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set, this holds members which help to config single rail multi step like delay between switch step, ramp up & ramp down step size in uv. - Added case to support SINGLE_RAIL_MULTI_STEP in volt_volt_policy_construct() based on boardobj type. - Added case to support SINGLE_RAIL_MULTI_STEP in volt_get_volt_policy_table() to read data from VBIOS table vbios_voltage_policy_table_1x_entry & extract to voltage_policy_single_rail_multi_step. - Added methods to forward single rail multi step data to PMU using below methods by assigning data read from VBIOS voltage_policy_single_rail_multi_step to nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set interface. volt_construct_volt_policy_single_rail_multi_step() volt_policy_pmu_data_init_sr_multi_step() volt_policy_pmu_data_init_single_rail() construct_volt_policy_single_rail() Change-Id: I17bc8c320777191611365ee63274c38ffe5ecbf7 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1660687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/bios.h | 13 +++++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 10 ++++++++++ 2 files changed, 23 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 75f8da35..86e009a3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -813,12 +813,15 @@ struct vbios_voltage_policy_table_1x_entry { u8 type; u32 param0; u32 param1; + u32 param2; + u32 param3; } __packed; #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ GENMASK(7, 0) @@ -839,6 +842,16 @@ struct vbios_voltage_policy_table_1x_entry { GENMASK(31, 24) #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 +#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ + GENMASK(15, 0) +#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0 +#define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_MASK \ + GENMASK(31, 0) +#define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0 +#define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_MASK \ + GENMASK(31, 0) +#define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0 + /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ GENMASK(15, 0) diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index 3b286139..313a3b2a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h @@ -104,6 +104,7 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { struct nv_pmu_boardobjgrp_e32 super; + u8 perf_core_vf_seq_policy_idx; }; struct nv_pmu_volt_volt_policy_boardobj_set { @@ -114,6 +115,13 @@ struct nv_pmu_volt_volt_policy_sr_boardobj_set { u8 rail_idx; }; +struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set { + struct nv_pmu_volt_volt_policy_sr_boardobj_set super; + u16 inter_switch_delay_us; + u32 ramp_up_step_size_uv; + u32 ramp_down_step_size_uv; +}; + struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { struct nv_pmu_volt_volt_policy_boardobj_set super; u8 rail_idx_master; @@ -138,6 +146,8 @@ union nv_pmu_volt_volt_policy_boardobj_set_union { struct nv_pmu_boardobj board_obj; struct nv_pmu_volt_volt_policy_boardobj_set super; struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; + struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set + single_rail_ms; struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; struct nv_pmu_volt_volt_policy_srms_boardobj_set split_rail_m_s; -- cgit v1.2.2