From 85f9729af4a05057b0d9f1e48542f6f9e3acecab Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Mon, 23 Apr 2018 16:52:43 +0530 Subject: gpu: nvgpu: vf inject changes - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 27 +++++++++++++++++----- drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 2 +- 2 files changed, 22 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index e0a3313b..dde85435 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h @@ -336,12 +336,24 @@ struct nv_pmu_clk_clk_domain_list { NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; }; +struct nv_pmu_clk_clk_domain_list_v1 { + u8 num_domains; + struct ctrl_clk_clk_domain_list_item_v1 clk_domains[ + NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; +}; + struct nv_pmu_clk_vf_change_inject { u8 flags; struct nv_pmu_clk_clk_domain_list clk_list; struct nv_pmu_volt_volt_rail_list volt_list; }; +struct nv_pmu_clk_vf_change_inject_v1 { + u8 flags; + struct nv_pmu_clk_clk_domain_list_v1 clk_list; + struct nv_pmu_volt_volt_rail_list_v1 volt_list; +}; + #define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) @@ -400,12 +412,14 @@ union nv_pmu_clk_clk_freq_controller_boardobj_set_union { NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); /* CLK CMD ID definitions. */ -#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_CLK_CMD_ID_RPC (0x00000001) +#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001) +#define NV_PMU_CLK_CMD_ID_RPC (0x00000000) #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) -#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) -#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) +#define NV_PMU_CLK_RPC_ID_LOAD (0x00000001) +#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000) +#define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002) + struct nv_pmu_clk_cmd_rpc { u8 cmd_type; @@ -432,13 +446,14 @@ struct nv_pmu_clk_rpc { flcn_status flcn_status; union { struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; + struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1; struct nv_pmu_clk_load clk_load; } params; }; /* CLK MSG ID definitions */ -#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_CLK_MSG_ID_RPC (0x00000001) +#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000001) +#define NV_PMU_CLK_MSG_ID_RPC (0x00000000) #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) struct nv_pmu_clk_msg_rpc { diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index 313a3b2a..b763c487 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h @@ -343,7 +343,7 @@ struct nv_pmu_volt_volt_rail_list { rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; }; -struct nv_pmu_volt_volt_rail_list_V1 { +struct nv_pmu_volt_volt_rail_list_v1 { u8 num_rails; struct ctrl_volt_volt_rail_list_item_v1 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; -- cgit v1.2.2