From 7a26ad57a7d2fc5cec4a0c8a8395c0c666d31cba Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 6 Feb 2019 16:23:11 -0800 Subject: gpu: nvgpu: enable platform atomic feature Support following changes related to platform atomic feature NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege, so atomic mode register bits cannot be updated from kernel code. atomic capability and atomic_sys_ncoh_mode bits are copied from fb mmu_ctrl to gpcs_mmu_ctrl register. new tu104 hal for fb_enable_nvlink function. bug 200580236 Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2013481 (cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1) Signed-off-by: Lakshmanan M Reviewed-on: https://git-master.nvidia.com/r/2274932 GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H Reviewed-by: Deepak Nibade Reviewed-by: Bibek Basu Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 54 +++++++++++++++++++++- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 10 +++- 2 files changed, 62 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 86bdaf28..fe35bb71 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -60,6 +60,22 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) { return 0x00100800U; } +static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) +{ + return U32(0x1U) << 25U; +} +static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) +{ + return 0x2000000U; +} +static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void) +{ + return U32(0x1U) << 26U; +} +static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void) +{ + return 0x0U; +} static inline u32 fb_mmu_ctrl_r(void) { return 0x00100c80U; @@ -76,6 +92,42 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { return (r >> 16U) & 0xffU; } +static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) +{ + return U32(0x3U) << 24U; +} +static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) +{ + return 0x2000000U; +} +static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) +{ + return U32(0x1U) << 27U; +} +static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void) +{ + return 0x0U; +} +static inline u32 fb_hshub_num_active_ltcs_r(void) +{ + return 0x001fbc20U; +} +static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) +{ + return U32(0x1U) << 25U; +} +static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) +{ + return 0x0U; +} +static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) +{ + return 0x2000000U; +} static inline u32 fb_priv_mmu_phy_secure_r(void) { return 0x00100ce4U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 36a7ebf5..01dc99d5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -4976,6 +4976,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { return 0x1U << 31U; } +static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) +{ + return U32(0x3U) << 24U; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) +{ + return U32(0x1U) << 27U; +} static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { return 0x00418890U; -- cgit v1.2.2