From 503d489dba278136ea0e4241d000018682989da5 Mon Sep 17 00:00:00 2001 From: Vaibhav Kachore Date: Tue, 3 Jul 2018 17:21:13 +0530 Subject: gpu: nvgpu: Initialize hwpm perfmons (engine_sel) - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995 Signed-off-by: Vaibhav Kachore Reviewed-on: https://git-master.nvidia.com/r/1770755 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index 268efc52..a7ba460e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -232,4 +232,28 @@ static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) { return 0x10U; } +static inline u32 perf_pmmsys_engine_sel_r(u32 i) +{ + return 0x0024006cU + i*512U; +} +static inline u32 perf_pmmsys_engine_sel__size_1_v(void) +{ + return 0x00000020U; +} +static inline u32 perf_pmmfbp_engine_sel_r(u32 i) +{ + return 0x0020006cU + i*512U; +} +static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) +{ + return 0x00000020U; +} +static inline u32 perf_pmmgpc_engine_sel_r(u32 i) +{ + return 0x0018006cU + i*512U; +} +static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) +{ + return 0x00000020U; +} #endif -- cgit v1.2.2