From 3f83528d769169fdaf25912f425226eaa07427f0 Mon Sep 17 00:00:00 2001 From: Vaibhav Kachore Date: Wed, 25 Jul 2018 17:12:38 +0530 Subject: gpu: nvgpu: correct parameters in set_pmm_register - This patch corrects parameters in set_pmm_registers - As FBP 6 and 7 are floorswept for GV100, GPU_LIT_NUM_FBPS should not be used - halify get_num_hwpm_perfmon and set_pmm_register Bug 2106999 Change-Id: Ib285b25d0c836c93b529dfe4e26c078159a3e6dd Signed-off-by: Vaibhav Kachore Reviewed-on: https://git-master.nvidia.com/r/1785620 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 4 ++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index fa31d0e1..a7fe1c2f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -330,6 +330,10 @@ struct gpu_ops { u64 gpu_va, u32 mode); void (*init_hwpm_pmm_register)(struct gk20a *g); + void (*get_num_hwpm_perfmon)(struct gk20a *g, u32 *num_sys_perfmon, + u32 *num_fbp_perfmon, u32 *num_gpc_perfmon); + void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val, + u32 num_chiplets, u32 num_perfmons); int (*dump_gr_regs)(struct gk20a *g, struct gk20a_debug_output *o); int (*update_pc_sampling)(struct channel_gk20a *ch, diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index a7ba460e..40107ee8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -60,6 +60,10 @@ static inline u32 perf_pmmgpc_perdomain_offset_v(void) { return 0x00000200U; } +static inline u32 perf_pmmsys_perdomain_offset_v(void) +{ + return 0x00000200U; +} static inline u32 perf_pmmgpc_base_v(void) { return 0x00180000U; -- cgit v1.2.2