From 34732a14b22f09d8f9d52f756612178f0313f120 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 14 Sep 2018 11:45:19 +0530 Subject: nvgpu: gpu: Support multiple tpc-pg masks. - TPC powergating should be done before calling gk20a_enable_gr_hw. gk20a_enable_gr_hw() issues a GR engine reset. Without this fix, enabling 1 TPC from each PES causes ctxsw timeout error while running GFX Benchmark. - Adds valid tpc-pg mask for 1/2/3/4 active TPC configs. TPC Config - TPC-MASK 4 TPC configuration - 0x0 3 TPC configuration - 0x1/0x2/0x4/0x8 2 TPC configuration - 0x5/0x9/0x6/0xa - We should not write to gr_fe_tpc_pesmask_r() as part of TPC-PG sequence. This register is for debug purpose only. Bug 200442360 Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1809772 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 2ebe0011..8d7ccfa8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -138,6 +138,8 @@ enum gk20a_cbc_op { #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) +#define MAX_TPC_PG_CONFIGS 3 + enum nvgpu_unit; enum nvgpu_flush_op; @@ -1592,7 +1594,7 @@ struct gk20a { u32 tpc_pg_mask; bool can_tpc_powergate; - u32 valid_tpc_mask; + u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS]; struct nvgpu_bios bios; bool bios_is_init; -- cgit v1.2.2