From 2dd9bb03dd56ca86b0e61b89fab38d38a58ecddf Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Mon, 27 Aug 2018 12:42:02 +0530 Subject: gpu: nvgpu: changing page_idx from int to u64 page_idx is an element of the struct nvgpu_semaphore_pool, defined in include/nvgpu/semaphore.h file. page_idx can not be negative so changing it from int to u64 and its related changes in various files. This also fixes MISRA 10.4 violations in these files. Jira NVGPU-992 Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1801632 Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h index 32a7e388..2b8a5fd1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h @@ -301,7 +301,7 @@ u64 nvgpu_sgt_alignment(struct gk20a *g, struct nvgpu_sgt *sgt); */ int nvgpu_mem_create_from_mem(struct gk20a *g, struct nvgpu_mem *dest, struct nvgpu_mem *src, - int start_page, int nr_pages); + u64 start_page, int nr_pages); /* * Really free a vidmem buffer. There's a fair amount of work involved in diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index 85175069..3239551f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h @@ -41,9 +41,9 @@ * Max number of channels that can be used is 512. This of course needs to be * fixed to be dynamic but still fast. */ -#define SEMAPHORE_POOL_COUNT 512 -#define SEMAPHORE_SIZE 16 -#define SEMAPHORE_SEA_GROWTH_RATE 32 +#define SEMAPHORE_POOL_COUNT 512U +#define SEMAPHORE_SIZE 16U +#define SEMAPHORE_SEA_GROWTH_RATE 32U struct nvgpu_semaphore_sea; @@ -84,7 +84,7 @@ struct nvgpu_semaphore_pool { struct nvgpu_list_node pool_list_entry; /* Node for list of pools. */ u64 gpu_va; /* GPU access to the pool. */ u64 gpu_va_ro; /* GPU access to the pool. */ - int page_idx; /* Index into sea bitmap. */ + u64 page_idx; /* Index into sea bitmap. */ DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE); -- cgit v1.2.2