From 10c3d4447d4206302f5d51695bf1f193255dd889 Mon Sep 17 00:00:00 2001 From: Ashish Srivastava Date: Tue, 20 Feb 2018 17:10:27 +0530 Subject: gpu: nvgpu: gv11b: enable RMW for gpu atomics Separate HAL added in gv11b and gv100 for init_gpc_mmu function. In gv11b HAL, RMW is enabled for gpu atomics as default. In gv100 HAL, GPC atomic capability mode will get set based on the FB MMU capability. If GPU is connected through NVLINK then mmu will be set to RMW mode, else it will be in L2 mode. Bug 200390336 Change-Id: I224934f83d1762ec864ef8da7265dd01d86893a0 Signed-off-by: Ashish Srivastava Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1735137 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 8 ++++++++ 2 files changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index 0f83d6ba..d2a73286 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -4028,6 +4028,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { return 0x1U << 31U; } +static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) +{ + return 0x3U << 24U; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) +{ + return 0x2000000U; +} static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { return 0x00418890U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 5de691a2..90994a53 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -4936,6 +4936,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { return 0x1U << 31U; } +static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) +{ + return 0x3U << 24U; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) +{ + return 0x2000000U; +} static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { return 0x00418890U; -- cgit v1.2.2