From 06f54be8c979720515d22e24cb4a20868af45f59 Mon Sep 17 00:00:00 2001 From: Amulya Date: Tue, 14 Aug 2018 10:30:46 +0530 Subject: gpu: nvgpu: Fix MISRA 10.1-Using boolean as a bit Fix violations where a boolean is used as an operand in bit-shift operations and is interpreted as a numerical value. JIRA NVGPU-649 Change-Id: I4494c3b69d0e53319331b47d0a4de0b3de279f4f Signed-off-by: Amulya Reviewed-on: https://git-master.nvidia.com/r/1799322 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy Reviewed-by: Amulya Murthyreddy Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h | 6 +++++- drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h | 6 +++++- drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h | 6 +++++- drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h | 6 +++++- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | 6 +++++- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 6 +++++- 6 files changed, 30 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/include') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h index 27fb5884..7b4d87b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -336,6 +336,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { return (v & 0x1U) << 24U; } +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} static inline u32 falcon_falcon_imemd_r(u32 i) { return 0x00000184U + i*16U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h index a17c9a9a..c5985685 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { return (v & 0x1U) << 24U; } +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} static inline u32 falcon_falcon_imemd_r(u32 i) { return 0x00000184U + i*16U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h index 6740b2a6..d899e3f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { return (v & 0x1U) << 24U; } +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} static inline u32 falcon_falcon_imemd_r(u32 i) { return 0x00000184U + i*16U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h index 918f262b..6dc401d6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { return (v & 0x1U) << 24U; } +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} static inline u32 falcon_falcon_imemd_r(u32 i) { return 0x00000184U + i*16U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h index 122956bb..3492d68c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { return (v & 0x1U) << 24U; } +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} static inline u32 falcon_falcon_imemd_r(u32 i) { return 0x00000184U + i*16U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 4bb8f2de..31e883e5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { return (v & 0x1U) << 24U; } +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} static inline u32 falcon_falcon_imemd_r(u32 i) { return 0x00000184U + i*16U; -- cgit v1.2.2