From 3a11883f7f4399ae8dffbea00c1842e3c2095937 Mon Sep 17 00:00:00 2001 From: Peng Liu Date: Tue, 30 Oct 2018 13:45:43 -0700 Subject: gpu: nvgpu: using pmu counters for load estimate PMU counters #0 and #4 are used to count total cycles and busy cycles. These counts are used by podgov to estimate GPU load. PMU idle intr status register is used to monitor overflow. Overflow rarely occurs because frequency governor reads and resets the counters at a high cadence. When overflow occurs, 100% work load is reported to frequency governor. Bug 1963732 Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69 Signed-off-by: Peng Liu Reviewed-on: https://git-master.nvidia.com/r/1939547 (cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149) Reviewed-on: https://git-master.nvidia.com/r/1979495 Reviewed-by: Aaron Tian Tested-by: Aaron Tian Reviewed-by: Rajkumar Kasirajan Tested-by: Rajkumar Kasirajan Reviewed-by: Bibek Basu GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h') diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index c16d44f1..295c6e95 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -880,6 +880,54 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) { return 0x0U; } +static inline u32 pwr_pmu_idle_threshold_r(u32 i) +{ + return 0x0010a8a0U + i*4U; +} +static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) +{ + return (v & 0x7fffffffU) << 0U; +} +static inline u32 pwr_pmu_idle_intr_r(void) +{ + return 0x0010a9e8U; +} +static inline u32 pwr_pmu_idle_intr_en_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) +{ + return 0x00000000U; +} +static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) +{ + return 0x00000001U; +} +static inline u32 pwr_pmu_idle_intr_status_r(void) +{ + return 0x0010a9ecU; +} +static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 pwr_pmu_idle_intr_status_intr_m(void) +{ + return U32(0x1U) << 0U; +} +static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) +{ + return 0x00000001U; +} +static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) +{ + return 0x00000001U; +} static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) { return 0x0010a9f0U + i*8U; -- cgit v1.2.2