From d029ad5d8d39e7f153b43ca9d60c0ed1f23c8037 Mon Sep 17 00:00:00 2001 From: Vinod Gopalakrishnakurup Date: Wed, 1 Aug 2018 15:51:41 -0700 Subject: Revert "gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer" This reverts commit 96d4842c0dbae051258408480b981ed034163c13. Change-Id: Ibcdf78b242c7bb9f17651b2bb9e23777c97cd436 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1790634 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index d0be7e82..5f66d741 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -407,7 +407,7 @@ static const struct gpu_ops gv11b_ops = { .handle_notify_pending = gk20a_gr_handle_notify_pending, .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, - .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, + .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, .decode_priv_addr = gr_gv11b_decode_priv_addr, .create_priv_addr_table = gr_gv11b_create_priv_addr_table, .get_pmm_per_chiplet_offset = -- cgit v1.2.2