From bbef4c6927a13a24821c43cb2b6af72f859f7deb Mon Sep 17 00:00:00 2001 From: David Ung Date: Fri, 24 Apr 2020 17:46:15 -0700 Subject: gpu: nvgpu: initialize masks for the perfmon counters 3 Initialize the perfmon counters #3 masks to be same values as ELPG. Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030, but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0. Bug 2833620 Change-Id: I3a424345aec6176a97dd20fb2c68a6e2faf955ad Signed-off-by: David Ung Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299 Reviewed-by: automaticguardword Reviewed-by: Alex Waterman Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 12 ++++++++++++ drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2f7b4abc..a2384fc8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -720,7 +720,7 @@ static const struct gpu_ops gv11b_ops = { .pmu_mutex_release = gk20a_pmu_mutex_release, .pmu_is_interrupted = gk20a_pmu_is_interrupted, .pmu_isr = gk20a_pmu_isr, - .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, + .pmu_init_perfmon_counter = gv11b_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 1001ba16..5e586ec2 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -30,6 +30,7 @@ #include #include +#include "gk20a/pmu_gk20a.h" #include "gp10b/pmu_gp10b.h" #include "gp106/pmu_gp106.h" @@ -440,6 +441,17 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, msg->msg.pg.msg_type); } +void gv11b_pmu_init_perfmon_counter(struct gk20a *g) +{ + u32 data; + + gk20a_pmu_init_perfmon_counter(g); + + /* assign same mask setting from GR ELPG to counter #3 */ + data = gk20a_readl(g, pwr_pmu_idle_mask_2_supp_r(0)); + gk20a_writel(g, pwr_pmu_idle_mask_2_r(3), data); +} + int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index 9cb6b222..06efa8f6 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -29,6 +29,7 @@ struct gk20a; bool gv11b_is_pmu_supported(struct gk20a *g); int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); +void gv11b_pmu_init_perfmon_counter(struct gk20a *g); int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); bool gv11b_is_lazy_bootstrap(u32 falcon_id); -- cgit v1.2.2