From aa05648fd6038b69d1ed841f33b24cf1875efd83 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 2 Jun 2017 09:58:23 -0700 Subject: gpu: nvgpu: gv11b: set up for enabling/handling hub intr -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 173 +++++++++++++++++++++++++++++--- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 12 ++- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 19 ++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 198 +++++++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 5 +- 5 files changed, 379 insertions(+), 28 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 21d8cba3..da7c7d4a 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -15,6 +15,9 @@ #include +#include +#include + #include "gk20a/gk20a.h" #include "gk20a/kind_gk20a.h" @@ -26,6 +29,7 @@ #include #include #include +#include #include #include @@ -205,6 +209,90 @@ static void gv11b_init_kind_attr(void) } } +u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, + unsigned int index) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_size_r(index)); + return fb_mmu_fault_buffer_size_enable_v(reg_val); +} + +void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, + unsigned int index, unsigned int state) +{ + u32 fault_status; + u32 reg_val; + + nvgpu_log_fn(g, " "); + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_size_r(index)); + if (state) { + if (gv11b_fb_is_fault_buf_enabled(g, index)) { + nvgpu_log_info(g, "fault buffer is already enabled"); + } else { + reg_val |= fb_mmu_fault_buffer_size_enable_true_f(); + gk20a_writel(g, fb_mmu_fault_buffer_size_r(index), + reg_val); + } + + } else { + struct nvgpu_timeout timeout; + u32 delay = GR_IDLE_CHECK_DEFAULT; + + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + + reg_val &= (~(fb_mmu_fault_buffer_size_enable_m())); + gk20a_writel(g, fb_mmu_fault_buffer_size_r(index), reg_val); + + fault_status = gk20a_readl(g, fb_mmu_fault_status_r()); + + do { + if (!(fault_status & fb_mmu_fault_status_busy_true_f())) + break; + /* + * Make sure fault buffer is disabled. + * This is to avoid accessing fault buffer by hw + * during the window BAR2 is being unmapped by s/w + */ + nvgpu_log_info(g, "fault status busy set, check again"); + fault_status = gk20a_readl(g, fb_mmu_fault_status_r()); + + nvgpu_usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "fault status busy set")); + } +} + +void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index) +{ + u32 addr_lo; + u32 addr_hi; + + nvgpu_log_fn(g, " "); + + gv11b_fb_fault_buf_set_state_hw(g, index, + FAULT_BUF_DISABLED); + + addr_lo = u64_lo32(g->mm.hw_fault_buf[index].gpu_va >> + ram_in_base_shift_v()); + addr_hi = u64_hi32(g->mm.hw_fault_buf[index].gpu_va); + + gk20a_writel(g, fb_mmu_fault_buffer_lo_r(index), + fb_mmu_fault_buffer_lo_addr_f(addr_lo)); + + gk20a_writel(g, fb_mmu_fault_buffer_hi_r(index), + fb_mmu_fault_buffer_hi_addr_f(addr_hi)); + + gk20a_writel(g, fb_mmu_fault_buffer_size_r(index), + fb_mmu_fault_buffer_size_val_f(g->ops.fifo.get_num_fifos(g)) | + fb_mmu_fault_buffer_size_overflow_intr_enable_f()); + + gv11b_fb_fault_buf_set_state_hw(g, index, FAULT_BUF_ENABLED); +} + static void gv11b_fb_intr_en_set(struct gk20a *g, unsigned int index, u32 mask) { @@ -230,15 +318,32 @@ static u32 gv11b_fb_get_hub_intr_clr_mask(struct gk20a *g, { u32 mask = 0; - if (intr_type == HUB_INTR_TYPE_ALL) { + if (intr_type & HUB_INTR_TYPE_OTHER) { + mask |= + fb_niso_intr_en_clr_mmu_other_fault_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_NONREPLAY) { + mask |= + fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(); + } + + if (intr_type & HUB_INTR_TYPE_REPLAY) { mask |= - fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(); - return mask; + fb_niso_intr_en_clr_mmu_replayable_fault_notify_m() | + fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(); } if (intr_type & HUB_INTR_TYPE_ECC_UNCORRECTED) { mask |= - fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(); + fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_ACCESS_COUNTER) { + mask |= + fb_niso_intr_en_clr_hub_access_counter_notify_m() | + fb_niso_intr_en_clr_hub_access_counter_error_m(); } return mask; @@ -249,15 +354,32 @@ static u32 gv11b_fb_get_hub_intr_en_mask(struct gk20a *g, { u32 mask = 0; - if (intr_type == HUB_INTR_TYPE_ALL) { + if (intr_type & HUB_INTR_TYPE_OTHER) { mask |= - fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(); - return mask; + fb_niso_intr_en_set_mmu_other_fault_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_NONREPLAY) { + mask |= + fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(); + } + + if (intr_type & HUB_INTR_TYPE_REPLAY) { + mask |= + fb_niso_intr_en_set_mmu_replayable_fault_notify_m() | + fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(); } if (intr_type & HUB_INTR_TYPE_ECC_UNCORRECTED) { mask |= - fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(); + fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_ACCESS_COUNTER) { + mask |= + fb_niso_intr_en_set_hub_access_counter_notify_m() | + fb_niso_intr_en_set_hub_access_counter_error_m(); } return mask; @@ -469,14 +591,17 @@ static void gv11b_fb_hub_isr(struct gk20a *g) u32 status; u32 niso_intr = gk20a_readl(g, fb_niso_intr_r()); - nvgpu_info(g, "enter hub isr, niso_intr = 0x%x", niso_intr); + nvgpu_info(g, "enter hub isr, niso_intr = 0x%08x", niso_intr); + + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); if (niso_intr & (fb_niso_intr_hub_access_counter_notify_pending_f() | fb_niso_intr_hub_access_counter_error_pending_f())) { nvgpu_info(g, "hub access counter notify/error"); - } else if (niso_intr & + } + if (niso_intr & fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f()) { nvgpu_info(g, "ecc uncorrected error notify"); @@ -501,9 +626,33 @@ static void gv11b_fb_hub_isr(struct gk20a *g) gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ECC_UNCORRECTED); - } else { - nvgpu_info(g, "mmu fault : TODO"); } + if (niso_intr & + (fb_niso_intr_mmu_other_fault_notify_m() | + fb_niso_intr_mmu_replayable_fault_notify_m() | + fb_niso_intr_mmu_replayable_fault_overflow_m() | + fb_niso_intr_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) { + + nvgpu_info(g, "mmu fault : No handling in place"); + + } + + nvgpu_mutex_release(&g->mm.hub_isr_mutex); +} + +bool gv11b_fb_mmu_fault_pending(struct gk20a *g) +{ + if (gk20a_readl(g, fb_niso_intr_r()) & + (fb_niso_intr_mmu_other_fault_notify_m() | + fb_niso_intr_mmu_ecc_uncorrected_error_notify_m() | + fb_niso_intr_mmu_replayable_fault_notify_m() | + fb_niso_intr_mmu_replayable_fault_overflow_m() | + fb_niso_intr_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) + return true; + + return false; } void gv11b_init_fb(struct gpu_ops *gops) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index eff3c25d..d8f5e145 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -40,9 +40,19 @@ struct gpu_ops; HUB_INTR_TYPE_ECC_UNCORRECTED | \ HUB_INTR_TYPE_ACCESS_COUNTER) +#define FAULT_TYPE_OTHER_AND_NONREPLAY 0 +#define FAULT_TYPE_REPLAY 1 + +void gv11b_init_fb(struct gpu_ops *gops); +u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, + unsigned int index); +void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, + unsigned int index, unsigned int state); +void gv11b_fb_nonreplay_fault_buf_configure_hw(struct gk20a *g); void gv11b_fb_enable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); -void gv11b_init_fb(struct gpu_ops *gops); +void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); +bool gv11b_fb_mmu_fault_pending(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 8b8fcea0..cc29f74a 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -30,6 +30,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g) gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | mc_intr_hub_pending_f() | @@ -38,20 +42,19 @@ static void mc_gv11b_intr_enable(struct gk20a *g) mc_intr_ltc_pending_f() | eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() | eng_intr_mask; + + /* TODO: Enable PRI faults for HUB ECC err intr */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); - /* TODO: Enable PRI faults for HUB ECC err intr */ - gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, - HUB_INTR_TYPE_ECC_UNCORRECTED); } static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index cc8dafa3..d6184cee 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -15,13 +15,21 @@ #include +#include +#include +#include + #include "gk20a/gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "mm_gv11b.h" +#include "fb_gv11b.h" #include +#include #define NVGPU_L3_ALLOC_BIT 36 @@ -46,12 +54,187 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { - if (gk20a_readl(g, fb_niso_intr_r()) & - (fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() | - fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f())) - return true; + return gv11b_fb_mmu_fault_pending(g); +} - return false; +static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +{ + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); + + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER | + HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); + + nvgpu_kfree(g, g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]); + + g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY] = NULL; + g->mm.fault_info[FAULT_TYPE_REPLAY] = NULL; + + nvgpu_mutex_release(&g->mm.hub_isr_mutex); + nvgpu_mutex_destroy(&g->mm.hub_isr_mutex); +} + +static int gv11b_mm_mmu_fault_info_buf_init(struct gk20a *g, + u32 *hub_intr_types) +{ + struct mmu_fault_info *fault_info_mem; + + fault_info_mem = nvgpu_kzalloc(g, sizeof(struct mmu_fault_info) * + FAULT_TYPE_NUM); + if (!fault_info_mem) { + nvgpu_log_info(g, "failed to alloc shadow fault info"); + return -ENOMEM; + } + /* shadow buffer for copying mmu fault info */ + g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY] = + &fault_info_mem[FAULT_TYPE_OTHER_AND_NONREPLAY]; + + g->mm.fault_info[FAULT_TYPE_REPLAY] = + &fault_info_mem[FAULT_TYPE_REPLAY]; + + *hub_intr_types |= HUB_INTR_TYPE_OTHER; + return 0; +} + +static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, + u32 *hub_intr_types) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + int err = 0; + size_t fb_size; + + /* Max entries take care of 1 entry used for full detection */ + fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * + gmmu_fault_buf_size_v(); + + err = nvgpu_dma_alloc_map_sys(vm, fb_size, + &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + if (err) { + nvgpu_err(g, + "Error in hw mmu fault buf [0] alloc in bar2 vm "); + /* Fault will be snapped in pri reg but not in buffer */ + return; + } + + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_TRUE; + *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; + + err = nvgpu_dma_alloc_map_sys(vm, fb_size, + &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + if (err) { + nvgpu_err(g, + "Error in hw mmu fault buf [1] alloc in bar2 vm "); + /* Fault will be snapped in pri reg but not in buffer */ + return; + } + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_TRUE; + *hub_intr_types |= HUB_INTR_TYPE_REPLAY; +} + +static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY | + HUB_INTR_TYPE_REPLAY); + + g->mm.hub_intr_types &= (~(HUB_INTR_TYPE_NONREPLAY | + HUB_INTR_TYPE_REPLAY)); + + if ((gv11b_fb_is_fault_buf_enabled(g, NONREPLAY_REG_INDEX))) { + gv11b_fb_fault_buf_set_state_hw(g, NONREPLAY_REG_INDEX, + FAULT_BUF_DISABLED); + } + + if ((gv11b_fb_is_fault_buf_enabled(g, REPLAY_REG_INDEX))) { + gv11b_fb_fault_buf_set_state_hw(g, REPLAY_REG_INDEX, + FAULT_BUF_DISABLED); + } + + if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + nvgpu_dma_unmap_free(vm, + &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + } + + if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + nvgpu_dma_unmap_free(vm, + &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + } +} + +static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + + gv11b_mm_mmu_hw_fault_buf_deinit(g); + + gk20a_free_inst_block(g, &mm->bar2.inst_block); + nvgpu_vm_put(mm->bar2.vm); +} + +static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g) +{ + if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX); + } + if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX); + } +} + +static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) +{ + int err; + + nvgpu_mutex_init(&g->mm.hub_isr_mutex); + + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + + g->mm.hub_intr_types = HUB_INTR_TYPE_ECC_UNCORRECTED; + + err = gv11b_mm_mmu_fault_info_buf_init(g, &g->mm.hub_intr_types); + + if (!err) + gv11b_mm_mmu_hw_fault_buf_init(g, &g->mm.hub_intr_types); + + return err; +} + +static int gv11b_init_mm_setup_hw(struct gk20a *g) +{ + int err = 0; + + nvgpu_log_fn(g, "start"); + + g->ops.fb.set_mmu_page_size(g); + g->ops.fb.init_hw(g); + + err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (err) + return err; + + if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) + return -EBUSY; + + err = gv11b_mm_mmu_fault_setup_sw(g); + if (!err) + gv11b_mm_mmu_fault_setup_hw(g); + + nvgpu_log_fn(g, "end"); + + return err; } void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) @@ -82,8 +265,11 @@ void gv11b_init_mm(struct gpu_ops *gops) gp10b_init_mm(gops); gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; gops->mm.l2_flush = gv11b_mm_l2_flush; gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; + gops->mm.fault_info_mem_destroy = + gv11b_mm_fault_info_mem_destroy; + gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; } diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index 4284b171..a887c7f4 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -1,6 +1,6 @@ /* * GV11B MM - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,6 +15,9 @@ #ifndef MM_GV11B_H #define MM_GV11B_H +#define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1 +#define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0 + struct gpu_ops; void gv11b_init_mm(struct gpu_ops *gops); -- cgit v1.2.2