From 9beefc45516097db2eabf2887ff66d3334ff9fde Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 19 Jan 2018 14:47:47 -0800 Subject: gpu: nvgpu: add fecs_host_int_enable hal This will be used to enable fecs interrupts per chip. Change-Id: Id99412ca1a9c4caad999c3458b0e9701515db4b9 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1642554 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 19 ++++++++++++++++--- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 3 files changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 857f4944..6b43fcc8 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -321,6 +321,19 @@ void gr_gv11b_enable_hww_exceptions(struct gk20a *g) gr_memfmt_hww_esr_reset_active_f()); } +void gr_gv11b_fecs_host_int_enable(struct gk20a *g) +{ + gk20a_writel(g, gr_fecs_host_int_enable_r(), + gr_fecs_host_int_enable_ctxsw_intr1_enable_f() | + gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() | + gr_fecs_host_int_enable_umimp_firmware_method_enable_f() | + gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | + gr_fecs_host_int_enable_watchdog_enable_f() | + gr_fecs_host_int_enable_flush_when_busy_enable_f() | + gr_fecs_host_int_enable_ecc_corrected_enable_f() | + gr_fecs_host_int_enable_ecc_uncorrected_enable_f()); +} + void gr_gv11b_enable_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -2249,13 +2262,13 @@ int gr_gv11b_handle_fecs_error(struct gk20a *g, u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); int ret; - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data); + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); /* Handle ECC errors */ gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); + ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data); + return ret; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 774afe56..157c567a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -133,6 +133,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, bool sm_debugger_attached, struct channel_gk20a *fault_ch, bool *early_exit, bool *ignore_debugger); +void gr_gv11b_fecs_host_int_enable(struct gk20a *g); int gr_gv11b_handle_fecs_error(struct gk20a *g, struct channel_gk20a *__ch, struct gr_gk20a_isr_data *isr_data); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 97660917..ec86d74c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -398,6 +398,7 @@ static const struct gpu_ops gv11b_ops = { gr_gv11b_get_max_gfxp_wfi_timeout_count, .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, + .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, }, .fb = { .reset = gv11b_fb_reset, -- cgit v1.2.2