From 34732a14b22f09d8f9d52f756612178f0313f120 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 14 Sep 2018 11:45:19 +0530 Subject: nvgpu: gpu: Support multiple tpc-pg masks. - TPC powergating should be done before calling gk20a_enable_gr_hw. gk20a_enable_gr_hw() issues a GR engine reset. Without this fix, enabling 1 TPC from each PES causes ctxsw timeout error while running GFX Benchmark. - Adds valid tpc-pg mask for 1/2/3/4 active TPC configs. TPC Config - TPC-MASK 4 TPC configuration - 0x0 3 TPC configuration - 0x1/0x2/0x4/0x8 2 TPC configuration - 0x5/0x9/0x6/0xa - We should not write to gr_fe_tpc_pesmask_r() as part of TPC-PG sequence. This register is for debug purpose only. Bug 200442360 Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1809772 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 21 --------------------- 1 file changed, 21 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 3dedc6b5..288bd583 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -73,16 +73,6 @@ */ #define GR_TPCS_INFO_FOR_MAPREGISTER 6 -/* - * There are 4 TPCs in GV11b ranging from TPC0 to TPC3 - * There are two PES in GV11b each controlling two TPCs - * PES0 is linked to TPC0 & TPC2 - * PES1 is linked to TPC1 & TPC3 - */ -#define TPC_MASK_FOR_PESID_0 (u32) 0x5 -#define TPC_MASK_FOR_PESID_1 (u32) 0xa - - bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -143,17 +133,6 @@ void gr_gv11b_powergate_tpc(struct gk20a *g) tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); } while (tpc_pg_status != g->tpc_pg_mask); - gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | - gr_fe_tpc_pesmask_action_write_f() | - gr_fe_tpc_pesmask_pesid_f(0) | - gr_fe_tpc_pesmask_gpcid_f(0) | - ((~g->tpc_pg_mask & (u32) 0xf) & TPC_MASK_FOR_PESID_0)); - gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | - gr_fe_tpc_pesmask_action_write_f() | - gr_fe_tpc_pesmask_pesid_f(1) | - gr_fe_tpc_pesmask_gpcid_f(0) | - ((~g->tpc_pg_mask & (u32) 0xf) & TPC_MASK_FOR_PESID_1)); - return; } -- cgit v1.2.2