From 2d0149c9abd74fd6bb59e076cfd46f49097e5662 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 23 Aug 2018 14:45:19 -0400 Subject: gpu: nvgpu: resolve MISRA 10.3 violations MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This value was then returned in a function defined by gpu_ops. This patch changes the return type for these gpu_ops to u64 and updates the functions that implement the functions and lastly the saved value. This removes the violation in this instance. JIRA NVGPU-647 Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1805588 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 22 +++++++++++----------- drivers/gpu/nvgpu/gv11b/regops_gv11b.h | 14 +++++++------- 2 files changed, 18 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index f84b5066..768674fe 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c @@ -1441,7 +1441,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { }; -static const u32 gv11b_global_whitelist_ranges_count = +static const u64 gv11b_global_whitelist_ranges_count = ARRAY_SIZE(gv11b_global_whitelist_ranges); /* context */ @@ -1449,24 +1449,24 @@ static const u32 gv11b_global_whitelist_ranges_count = /* runcontrol */ static const u32 gv11b_runcontrol_whitelist[] = { }; -static const u32 gv11b_runcontrol_whitelist_count = +static const u64 gv11b_runcontrol_whitelist_count = ARRAY_SIZE(gv11b_runcontrol_whitelist); static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = { }; -static const u32 gv11b_runcontrol_whitelist_ranges_count = +static const u64 gv11b_runcontrol_whitelist_ranges_count = ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges); /* quad ctl */ static const u32 gv11b_qctl_whitelist[] = { }; -static const u32 gv11b_qctl_whitelist_count = +static const u64 gv11b_qctl_whitelist_count = ARRAY_SIZE(gv11b_qctl_whitelist); static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = { }; -static const u32 gv11b_qctl_whitelist_ranges_count = +static const u64 gv11b_qctl_whitelist_ranges_count = ARRAY_SIZE(gv11b_qctl_whitelist_ranges); const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) @@ -1474,7 +1474,7 @@ const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) return gv11b_global_whitelist_ranges; } -int gv11b_get_global_whitelist_ranges_count(void) +u64 gv11b_get_global_whitelist_ranges_count(void) { return gv11b_global_whitelist_ranges_count; } @@ -1484,7 +1484,7 @@ const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void) return gv11b_global_whitelist_ranges; } -int gv11b_get_context_whitelist_ranges_count(void) +u64 gv11b_get_context_whitelist_ranges_count(void) { return gv11b_global_whitelist_ranges_count; } @@ -1494,7 +1494,7 @@ const u32 *gv11b_get_runcontrol_whitelist(void) return gv11b_runcontrol_whitelist; } -int gv11b_get_runcontrol_whitelist_count(void) +u64 gv11b_get_runcontrol_whitelist_count(void) { return gv11b_runcontrol_whitelist_count; } @@ -1504,7 +1504,7 @@ const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void) return gv11b_runcontrol_whitelist_ranges; } -int gv11b_get_runcontrol_whitelist_ranges_count(void) +u64 gv11b_get_runcontrol_whitelist_ranges_count(void) { return gv11b_runcontrol_whitelist_ranges_count; } @@ -1514,7 +1514,7 @@ const u32 *gv11b_get_qctl_whitelist(void) return gv11b_qctl_whitelist; } -int gv11b_get_qctl_whitelist_count(void) +u64 gv11b_get_qctl_whitelist_count(void) { return gv11b_qctl_whitelist_count; } @@ -1524,7 +1524,7 @@ const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void) return gv11b_qctl_whitelist_ranges; } -int gv11b_get_qctl_whitelist_ranges_count(void) +u64 gv11b_get_qctl_whitelist_ranges_count(void) { return gv11b_qctl_whitelist_ranges_count; } diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h index 0ee2edfe..b605c0a6 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h @@ -2,7 +2,7 @@ * * Tegra GV11B GPU Driver Register Ops * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,17 +26,17 @@ #define __REGOPS_GV11B_H_ const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void); -int gv11b_get_global_whitelist_ranges_count(void); +u64 gv11b_get_global_whitelist_ranges_count(void); const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void); -int gv11b_get_context_whitelist_ranges_count(void); +u64 gv11b_get_context_whitelist_ranges_count(void); const u32 *gv11b_get_runcontrol_whitelist(void); -int gv11b_get_runcontrol_whitelist_count(void); +u64 gv11b_get_runcontrol_whitelist_count(void); const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void); -int gv11b_get_runcontrol_whitelist_ranges_count(void); +u64 gv11b_get_runcontrol_whitelist_ranges_count(void); const u32 *gv11b_get_qctl_whitelist(void); -int gv11b_get_qctl_whitelist_count(void); +u64 gv11b_get_qctl_whitelist_count(void); const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void); -int gv11b_get_qctl_whitelist_ranges_count(void); +u64 gv11b_get_qctl_whitelist_ranges_count(void); int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); #endif /* __REGOPS_GV11B_H_ */ -- cgit v1.2.2