From 2328d305b7c9437aa467922086b9fcfc0a4169ba Mon Sep 17 00:00:00 2001 From: Amulya Date: Mon, 6 Aug 2018 10:37:32 +0530 Subject: gpu: nvgpu: MISRA 10.4 enum fixes MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 9 +++++---- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 7 ++++--- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4327e087..058a21e5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -4138,8 +4138,9 @@ void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); } -int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, - u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, + u32 *broadcast_flags) { u32 gpc_addr; u32 tpc_addr; @@ -4702,7 +4703,7 @@ int gr_gv11b_handle_ssync_hww(struct gk20a *g) * type and numbers */ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, /* enum ctxsw_addr_type */ + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags) { @@ -4849,7 +4850,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, u32 *priv_addr_table, u32 *num_registers) { - int addr_type; /*enum ctxsw_addr_type */ + enum ctxsw_addr_type addr_type; u32 gpc_num, tpc_num, ppc_num, be_num; u32 priv_addr, gpc_addr; u32 broadcast_flags; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9c680827..0a8a536c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -217,8 +217,9 @@ bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr); bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr); void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, u32 *egpc_num, u32 *etpc_num); -int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, - u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, + u32 *broadcast_flags); void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, u32 gpc, u32 tpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t); u32 gv11b_gr_get_egpc_base(struct gk20a *g); @@ -242,7 +243,7 @@ u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); u32 gr_gv11b_get_pmm_per_chiplet_offset(void); int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags); int gr_gv11b_create_priv_addr_table(struct gk20a *g, -- cgit v1.2.2