From 67b54c3c76cfa488e1d102e5c74a32b3aaba9287 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 12:25:08 -0800 Subject: gpu: nvgpu: legacy support with subcontext gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 147 +++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/subctx_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c new file mode 100644 index 00000000..3acc53f6 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -0,0 +1,147 @@ +/* + * Volta GPU series Subcontext + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/semaphore_gk20a.h" +#include "gv11b/subctx_gv11b.h" +#include "gv11b/hw_ram_gv11b.h" +#include "gv11b/hw_ctxsw_prog_gv11b.h" + +static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, + struct mem_desc *inst_block); + +void gv11b_free_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct gk20a *g = c->g; + + gk20a_dbg_fn(""); + + if (ctx->mem.gpu_va) { + gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, + ctx->mem.size, gk20a_mem_flag_none); + + gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &ctx->mem); + } +} + +int gv11b_alloc_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct gk20a *g = c->g; + int ret = 0; + + gk20a_dbg_fn(""); + + if (ctx->mem.gpu_va == 0) { + ret = gk20a_gmmu_alloc_attr_sys(g, + DMA_ATTR_NO_KERNEL_MAPPING, + ctxsw_prog_fecs_header_v(), + &ctx->mem); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to allocate sub ctx header"); + return ret; + } + ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, + &ctx->mem.sgt, + ctx->mem.size, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + gk20a_mem_flag_none, true, + ctx->mem.aperture); + if (!ctx->mem.gpu_va) { + gk20a_err(dev_from_gk20a(g), + "failed to map ctx header"); + gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, + &ctx->mem); + return -ENOMEM; + } + /* Now clear the buffer */ + if (gk20a_mem_begin(g, &ctx->mem)) + return -ENOMEM; + + gk20a_memset(g, &ctx->mem, 0, 0, ctx->mem.size); + gk20a_mem_end(g, &ctx->mem); + + gv11b_init_subcontext_pdb(c, &c->inst_block); + + } + return ret; +} + +static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, + struct mem_desc *inst_block) +{ + struct gk20a *g = c->g; + struct vm_gk20a *vm; + u64 pdb_addr, pdb_addr_lo, pdb_addr_hi; + u32 format_word; + u32 lo, hi; + + gk20a_dbg_fn(""); + /* load main pdb as veid0 pdb also */ + vm = c->vm; + pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.sgt->sgl, 0); + pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); + pdb_addr_hi = u64_hi32(pdb_addr); + format_word = ram_in_sc_page_dir_base_target_f( + ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | + ram_in_sc_page_dir_base_vol_f( + ram_in_sc_page_dir_base_vol_true_v(), 0) | + ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | + ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | + ram_in_sc_use_ver2_pt_format_f(1, 0) | + ram_in_sc_big_page_size_f(1, 0) | + ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); + lo = ram_in_sc_page_dir_base_vol_0_w(); + hi = ram_in_sc_page_dir_base_hi_0_w(); + gk20a_mem_wr32(g, inst_block, lo, format_word); + gk20a_mem_wr32(g, inst_block, hi, pdb_addr_hi); + + /* make subcontext0 address space to valid */ + /* TODO fix proper hw register definations */ + gk20a_mem_wr32(g, inst_block, 166, 0x1); + gk20a_mem_wr32(g, inst_block, 167, 0); + gk20a_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), + ram_in_engine_wfi_veid_f(0)); + +} + +int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct mem_desc *gr_mem; + struct gk20a *g = c->g; + int ret = 0; + u32 addr_lo, addr_hi; + + addr_lo = u64_lo32(gpu_va); + addr_hi = u64_hi32(gpu_va); + + gr_mem = &ctx->mem; + g->ops.mm.l2_flush(g, true); + if (gk20a_mem_begin(g, gr_mem)) + return -ENOMEM; + + gk20a_mem_wr(g, gr_mem, + ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); + gk20a_mem_wr(g, gr_mem, + ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); + gk20a_mem_end(g, gr_mem); + return ret; +} -- cgit v1.2.2 From 4f3871309d5216b50179feed8f8024193b2224cf Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 13 Jan 2017 13:34:24 -0800 Subject: gpu: nvgpu: gv11b: restore golden context Restore golden context correctly with subcontext header. Increase subctx header size to hold complete golden context. Also fill function pointer for freeing context header. Bug 1834201 Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1282440 Reviewed-by: Alex Waterman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 3acc53f6..b0d0a192 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -44,6 +44,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; struct gk20a *g = c->g; + struct gr_gk20a *gr = &g->gr; int ret = 0; gk20a_dbg_fn(""); @@ -51,7 +52,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (ctx->mem.gpu_va == 0) { ret = gk20a_gmmu_alloc_attr_sys(g, DMA_ATTR_NO_KERNEL_MAPPING, - ctxsw_prog_fecs_header_v(), + gr->ctx_vars.golden_image_size, &ctx->mem); if (ret) { gk20a_err(dev_from_gk20a(g), -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index b0d0a192..02683d8b 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -1,7 +1,7 @@ /* * Volta GPU series Subcontext * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,9 +18,11 @@ #include "gk20a/gk20a.h" #include "gk20a/semaphore_gk20a.h" + #include "gv11b/subctx_gv11b.h" -#include "gv11b/hw_ram_gv11b.h" -#include "gv11b/hw_ctxsw_prog_gv11b.h" + +#include +#include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct mem_desc *inst_block); -- cgit v1.2.2 From edad02b1b0071aa9fa0eac53d275e08a0051dca1 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 10 Feb 2017 16:15:42 -0800 Subject: gpu: nvgpu: Organize semaphore_gk20a.[ch] t19x version. Bug 1799159 Change-Id: I5e4c2a5341909d2e366ebc15adb4cdce70d695c7 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1303264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 02683d8b..63cce491 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -17,7 +17,6 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/semaphore_gk20a.h" #include "gv11b/subctx_gv11b.h" -- cgit v1.2.2 From e83372e0cc78a16777f0d2f43936e772f40308d2 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Tue, 14 Mar 2017 13:37:58 +0200 Subject: gpu: nvgpu: gv11b: abstract away dma alloc attrs Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct mem_desc now. Bug 1853519 Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1321314 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 63cce491..6344b5fb 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -37,7 +37,7 @@ void gv11b_free_subctx_header(struct channel_gk20a *c) gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, ctx->mem.size, gk20a_mem_flag_none); - gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &ctx->mem); + gk20a_gmmu_free(g, &ctx->mem); } } @@ -51,8 +51,8 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gk20a_dbg_fn(""); if (ctx->mem.gpu_va == 0) { - ret = gk20a_gmmu_alloc_attr_sys(g, - DMA_ATTR_NO_KERNEL_MAPPING, + ret = gk20a_gmmu_alloc_flags_sys(g, + NVGPU_DMA_NO_KERNEL_MAPPING, gr->ctx_vars.golden_image_size, &ctx->mem); if (ret) { @@ -69,8 +69,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (!ctx->mem.gpu_va) { gk20a_err(dev_from_gk20a(g), "failed to map ctx header"); - gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, - &ctx->mem); + gk20a_gmmu_free(g, &ctx->mem); return -ENOMEM; } /* Now clear the buffer */ -- cgit v1.2.2 From 633d331ae2db50fbcce829fe324c19fc44b82c24 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:00:24 -0700 Subject: gpu: nvgpu: Rename gk20a_mem_* functions Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: I5a1180c9a08d33c3dfc361ce8579c3c767fa5656 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326193 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 6344b5fb..8bf0631e 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -73,11 +73,11 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) return -ENOMEM; } /* Now clear the buffer */ - if (gk20a_mem_begin(g, &ctx->mem)) + if (nvgpu_mem_begin(g, &ctx->mem)) return -ENOMEM; - gk20a_memset(g, &ctx->mem, 0, 0, ctx->mem.size); - gk20a_mem_end(g, &ctx->mem); + nvgpu_memset(g, &ctx->mem, 0, 0, ctx->mem.size); + nvgpu_mem_end(g, &ctx->mem); gv11b_init_subcontext_pdb(c, &c->inst_block); @@ -111,14 +111,14 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); lo = ram_in_sc_page_dir_base_vol_0_w(); hi = ram_in_sc_page_dir_base_hi_0_w(); - gk20a_mem_wr32(g, inst_block, lo, format_word); - gk20a_mem_wr32(g, inst_block, hi, pdb_addr_hi); + nvgpu_mem_wr32(g, inst_block, lo, format_word); + nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); /* make subcontext0 address space to valid */ /* TODO fix proper hw register definations */ - gk20a_mem_wr32(g, inst_block, 166, 0x1); - gk20a_mem_wr32(g, inst_block, 167, 0); - gk20a_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), + nvgpu_mem_wr32(g, inst_block, 166, 0x1); + nvgpu_mem_wr32(g, inst_block, 167, 0); + nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), ram_in_engine_wfi_veid_f(0)); } @@ -136,13 +136,13 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) gr_mem = &ctx->mem; g->ops.mm.l2_flush(g, true); - if (gk20a_mem_begin(g, gr_mem)) + if (nvgpu_mem_begin(g, gr_mem)) return -ENOMEM; - gk20a_mem_wr(g, gr_mem, + nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); - gk20a_mem_wr(g, gr_mem, + nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); - gk20a_mem_end(g, gr_mem); + nvgpu_mem_end(g, gr_mem); return ret; } -- cgit v1.2.2 From c876bec8bab5a1e4d6dea529700ef19c5eac5e64 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:01:14 -0700 Subject: gpu: nvgpu: rename mem_desc to nvgpu_mem $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 8bf0631e..757baa6e 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -24,7 +24,7 @@ #include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, - struct mem_desc *inst_block); + struct nvgpu_mem *inst_block); void gv11b_free_subctx_header(struct channel_gk20a *c) { @@ -86,7 +86,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) } static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, - struct mem_desc *inst_block) + struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; struct vm_gk20a *vm; @@ -126,7 +126,7 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; - struct mem_desc *gr_mem; + struct nvgpu_mem *gr_mem; struct gk20a *g = c->g; int ret = 0; u32 addr_lo, addr_hi; -- cgit v1.2.2 From 26159aed046393e5d01060323a76f838d2f5bba3 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 4 Apr 2017 23:59:09 +0100 Subject: gpu: nvgpu: Move DMA API to dma.h Handle gv11b specific of gpu: nvgpu: Move DMA API to dma.h In the main nvgpu repository. JIRA NVGPU-12 Change-Id: I9645c4eedc5f61585d15caeee54db92bc4cca079 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1455212 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 757baa6e..a2b7de1c 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -16,6 +16,8 @@ * this program. */ +#include + #include "gk20a/gk20a.h" #include "gv11b/subctx_gv11b.h" -- cgit v1.2.2 From 1a426c981c4fa2816d969b27163ab2dbc2fa4e89 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 5 Apr 2017 00:08:52 +0100 Subject: gpu: nvgpu: Rename nvgpu DMA APIs gv11b changes to go along with gpu: nvgpu: Rename nvgpu DMA APIs In the main nvgpu repo. JIRA NVGPU-12 Change-Id: I5e28b13448d171e1511ace0842e53700385f8489 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1455213 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index a2b7de1c..8b322296 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -39,7 +39,7 @@ void gv11b_free_subctx_header(struct channel_gk20a *c) gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, ctx->mem.size, gk20a_mem_flag_none); - gk20a_gmmu_free(g, &ctx->mem); + nvgpu_dma_free(g, &ctx->mem); } } @@ -53,7 +53,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gk20a_dbg_fn(""); if (ctx->mem.gpu_va == 0) { - ret = gk20a_gmmu_alloc_flags_sys(g, + ret = nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING, gr->ctx_vars.golden_image_size, &ctx->mem); @@ -71,7 +71,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (!ctx->mem.gpu_va) { gk20a_err(dev_from_gk20a(g), "failed to map ctx header"); - gk20a_gmmu_free(g, &ctx->mem); + nvgpu_dma_free(g, &ctx->mem); return -ENOMEM; } /* Now clear the buffer */ -- cgit v1.2.2 From 7fe4b6572ba80dda58d513969b69e22437901077 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Apr 2017 11:09:13 -0700 Subject: gpu: nvgpu: gv11b: Use new error macros gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8c0d8944f625e3c5b16a9f5a2a59d95a680f4e55 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1459822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 8b322296..4d68926f 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -16,12 +16,13 @@ * this program. */ -#include - #include "gk20a/gk20a.h" #include "gv11b/subctx_gv11b.h" +#include +#include + #include #include @@ -58,8 +59,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gr->ctx_vars.golden_image_size, &ctx->mem); if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to allocate sub ctx header"); + nvgpu_err(g, "failed to allocate sub ctx header"); return ret; } ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, @@ -69,8 +69,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gk20a_mem_flag_none, true, ctx->mem.aperture); if (!ctx->mem.gpu_va) { - gk20a_err(dev_from_gk20a(g), - "failed to map ctx header"); + nvgpu_err(g, "failed to map ctx header"); nvgpu_dma_free(g, &ctx->mem); return -ENOMEM; } -- cgit v1.2.2 From 7b5b4fc84ff0067fb0e7b5a3b86a4b16784e8ffa Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 9 Mar 2017 11:30:14 -0800 Subject: gpu: nvgpu: gv11b: function to get max veid Defined function to get max number of subcontexs supported and used it where max subcontext count required. JIRA GV11B-23 Change-Id: I4f6307162486bab1e91cbf66abfee7763c70fe7b Signed-off-by: seshendra Gadagottu Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1318146 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 4d68926f..c3ff9185 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -25,6 +25,7 @@ #include #include +#include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block); @@ -147,3 +148,10 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) nvgpu_mem_end(g, gr_mem); return ret; } + +int gv11b_get_max_subctx_count(struct gk20a *g) +{ + u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); + + return gr_pri_fe_chip_def_info_max_veid_count_v(data); +} -- cgit v1.2.2 From 7872900486bd31cf186930848adec46d0a13b68a Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 17 Apr 2017 21:20:19 +0100 Subject: gpu: nvgpu: Move Linux nvgpu_mem fields t19x part for this change in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I31116b4241076b39a6638273281630a1527bcd35 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1464109 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index c3ff9185..dcf69adf 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -64,7 +64,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) return ret; } ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, - &ctx->mem.sgt, + &ctx->mem.priv.sgt, ctx->mem.size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, true, @@ -99,7 +99,7 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, gk20a_dbg_fn(""); /* load main pdb as veid0 pdb also */ vm = c->vm; - pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.sgt->sgl, 0); + pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.priv.sgt->sgl, 0); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( -- cgit v1.2.2 From 44dcc5a53fabc68a32f16a1a3a46a2582b5b192b Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 17 Apr 2017 22:16:00 +0100 Subject: gpu: nvgpu: Separate GMMU out of mm_gk20a.c t19x version of same named patch in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I0b176577c0edcdcc587f22a6908045a960f830e2 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1464111 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index dcf69adf..6aa58337 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -38,8 +39,7 @@ void gv11b_free_subctx_header(struct channel_gk20a *c) gk20a_dbg_fn(""); if (ctx->mem.gpu_va) { - gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, - ctx->mem.size, gk20a_mem_flag_none); + nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); nvgpu_dma_free(g, &ctx->mem); } @@ -63,8 +63,8 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) nvgpu_err(g, "failed to allocate sub ctx header"); return ret; } - ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, - &ctx->mem.priv.sgt, + ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, + &ctx->mem, ctx->mem.size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, true, -- cgit v1.2.2 From 492c7cc198f3315b468fa3d612d894edf2bb5e89 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 19 Jun 2017 17:40:45 -0700 Subject: gpu: nvgpu: gv11b: make subcontext mappings non-cacheable Without non-cacheable, gpu filled subcontext data not visible to cpu without additional l2 flush. Similarly, there will be issues where cpu updates to subcontext header will not visible to gpu without additional l2 flush. Making subcontext header mapping non-cacheable fixes this issue. Bug 1937331 Change-Id: I8e25b7cac165e7481eec7c9f1f93bc7992183c46 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1505283 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 6aa58337..79ed0d1e 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -66,7 +66,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, &ctx->mem, ctx->mem.size, - NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_FALSE, gk20a_mem_flag_none, true, ctx->mem.aperture); if (!ctx->mem.gpu_va) { -- cgit v1.2.2 From 6d758eb81bcbff4e50df5c9fa67a369a4e1f2074 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 29 Jun 2017 15:59:05 -0700 Subject: gpu: nvgpu: gv11b: support for full subcontext Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 90 +++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 33 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 79ed0d1e..cb042f87 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -31,12 +31,17 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block); +static void gv11b_subctx_commit_valid_mask(struct channel_gk20a *c, + struct nvgpu_mem *inst_block); +static void gv11b_subctx_commit_pdb(struct channel_gk20a *c, + struct nvgpu_mem *inst_block); + void gv11b_free_subctx_header(struct channel_gk20a *c) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; struct gk20a *g = c->g; - gk20a_dbg_fn(""); + nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header"); if (ctx->mem.gpu_va) { nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); @@ -52,7 +57,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) struct gr_gk20a *gr = &g->gr; int ret = 0; - gk20a_dbg_fn(""); + nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); if (ctx->mem.gpu_va == 0) { ret = nvgpu_dma_alloc_flags_sys(g, @@ -82,7 +87,6 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) nvgpu_mem_end(g, &ctx->mem); gv11b_init_subcontext_pdb(c, &c->inst_block); - } return ret; } @@ -91,37 +95,13 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; - struct vm_gk20a *vm; - u64 pdb_addr, pdb_addr_lo, pdb_addr_hi; - u32 format_word; - u32 lo, hi; - gk20a_dbg_fn(""); - /* load main pdb as veid0 pdb also */ - vm = c->vm; - pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.priv.sgt->sgl, 0); - pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); - pdb_addr_hi = u64_hi32(pdb_addr); - format_word = ram_in_sc_page_dir_base_target_f( - ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | - ram_in_sc_page_dir_base_vol_f( - ram_in_sc_page_dir_base_vol_true_v(), 0) | - ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | - ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | - ram_in_sc_use_ver2_pt_format_f(1, 0) | - ram_in_sc_big_page_size_f(1, 0) | - ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); - lo = ram_in_sc_page_dir_base_vol_0_w(); - hi = ram_in_sc_page_dir_base_hi_0_w(); - nvgpu_mem_wr32(g, inst_block, lo, format_word); - nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); - - /* make subcontext0 address space to valid */ - /* TODO fix proper hw register definations */ - nvgpu_mem_wr32(g, inst_block, 166, 0x1); - nvgpu_mem_wr32(g, inst_block, 167, 0); + gv11b_subctx_commit_pdb(c, inst_block); + gv11b_subctx_commit_valid_mask(c, inst_block); + + nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), - ram_in_engine_wfi_veid_f(0)); + ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); } @@ -149,7 +129,51 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) return ret; } -int gv11b_get_max_subctx_count(struct gk20a *g) +void gv11b_subctx_commit_valid_mask(struct channel_gk20a *c, + struct nvgpu_mem *inst_block) +{ + struct gk20a *g = c->g; + + /* Make all subctx pdbs valid */ + nvgpu_mem_wr32(g, inst_block, 166, 0xffffffff); + nvgpu_mem_wr32(g, inst_block, 167, 0xffffffff); +} + +void gv11b_subctx_commit_pdb(struct channel_gk20a *c, + struct nvgpu_mem *inst_block) +{ + struct gk20a *g = c->g; + u32 lo, hi; + u32 subctx_id = 0; + u32 format_word; + u32 pdb_addr_lo, pdb_addr_hi; + u64 pdb_addr; + + pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem.priv.sgt->sgl, 0); + pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); + pdb_addr_hi = u64_hi32(pdb_addr); + format_word = ram_in_sc_page_dir_base_target_f( + ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | + ram_in_sc_page_dir_base_vol_f( + ram_in_sc_page_dir_base_vol_true_v(), 0) | + ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | + ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | + ram_in_sc_use_ver2_pt_format_f(1, 0) | + ram_in_sc_big_page_size_f(1, 0) | + ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); + nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", + format_word, pdb_addr_hi); + for (subctx_id = 0; subctx_id < gv11b_get_max_subctx_count(g); + subctx_id++) { + lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); + hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); + nvgpu_mem_wr32(g, inst_block, lo, format_word); + nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); + } +} + + +u32 gv11b_get_max_subctx_count(struct gk20a *g) { u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); -- cgit v1.2.2 From 6745200c6f5d5336bf3fbca6ed00794c2deec5ec Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 8 Jun 2017 15:05:19 -0700 Subject: gpu: nvgpu: Implement PD packing Necessary Volta changes for equivalent change in nvgpu. JIRA NVGPU-30 Change-Id: I541d6d6005bc7ea0bfb654d0f5f5554e46afc510 Signed-off-by: Alex Waterman Reviewed-on: https://git-master/r/1506611 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index cb042f87..68e969d0 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -149,7 +149,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, u32 pdb_addr_lo, pdb_addr_hi; u64 pdb_addr; - pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem.priv.sgt->sgl, 0); + pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem->priv.sgt->sgl, 0); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( -- cgit v1.2.2 From 971c90e3b6b7f1e3f5dff67ccd701c99c1b0f7b5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 11 May 2017 09:42:44 -0700 Subject: gpu: nvgpu: gv11b: set replay fault for tex and gcc This is to enable replay fault from tex and gcc engines JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I0cc8a59499da9eb056d19ee8d6cd33a94e3f0835 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1493407 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 68e969d0..bda36216 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -156,8 +156,8 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | ram_in_sc_page_dir_base_vol_f( ram_in_sc_page_dir_base_vol_true_v(), 0) | - ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | - ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | + ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) | + ram_in_sc_page_dir_base_fault_replay_gcc_f(1, 0) | ram_in_sc_use_ver2_pt_format_f(1, 0) | ram_in_sc_big_page_size_f(1, 0) | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); -- cgit v1.2.2 From 5a5792d911d99a08663c59f74c552883804780f3 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 8 Jun 2017 15:05:19 -0700 Subject: gpu: nvgpu: Remove mm.get_iova_addr Volta changes for equivalent change on nvgpu. JIRA NVGPU-30 Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1530863 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index bda36216..72a66530 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -143,13 +143,14 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; + struct vm_gk20a *vm = c->vm; u32 lo, hi; u32 subctx_id = 0; u32 format_word; u32 pdb_addr_lo, pdb_addr_hi; u64 pdb_addr; - pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem->priv.sgt->sgl, 0); + pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( -- cgit v1.2.2 From 3197a918d5052c71ad854f6b22fdb35bfe7cebe2 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 10 Aug 2017 16:34:16 -0700 Subject: gpu: nvgpu: gv11b: add max_subctx_count to g->fifo.t19x - For better performance. It used to read register every time referencing max_subctx_count. - Avoid reading registers for vgpu. Jira VFND-3797 Change-Id: Id6e6b15a0d9a035795e8a9a2c6bb63524c5eb544 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1537009 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 72a66530..4f64843c 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -26,7 +26,6 @@ #include #include -#include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block); @@ -143,6 +142,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; + struct fifo_gk20a *f = &g->fifo; struct vm_gk20a *vm = c->vm; u32 lo, hi; u32 subctx_id = 0; @@ -164,19 +164,10 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", format_word, pdb_addr_hi); - for (subctx_id = 0; subctx_id < gv11b_get_max_subctx_count(g); - subctx_id++) { + for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) { lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); nvgpu_mem_wr32(g, inst_block, lo, format_word); nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); } } - - -u32 gv11b_get_max_subctx_count(struct gk20a *g) -{ - u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); - - return gr_pri_fe_chip_def_info_max_veid_count_v(data); -} -- cgit v1.2.2 From b454d30d89d3a3830fc44039ec543286444e9e13 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 14 Sep 2017 16:32:11 -0700 Subject: gpu: nvgpu: gv11b: enable per veid header for subctx Enable per veid header mode for subcontext header. Allocated only context header size for subcontext header. Bug 1958308 Change-Id: I6b45987eed968252326a366650fefd807975b70f Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1562681 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 4f64843c..ee89ecc2 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -53,7 +53,6 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; struct gk20a *g = c->g; - struct gr_gk20a *gr = &g->gr; int ret = 0; nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); @@ -61,7 +60,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (ctx->mem.gpu_va == 0) { ret = nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING, - gr->ctx_vars.golden_image_size, + ctxsw_prog_fecs_header_v(), &ctx->mem); if (ret) { nvgpu_err(g, "failed to allocate sub ctx header"); @@ -124,6 +123,10 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); + + nvgpu_mem_wr(g, gr_mem, + ctxsw_prog_main_image_ctl_o(), + ctxsw_prog_main_image_ctl_type_per_veid_header_v()); nvgpu_mem_end(g, gr_mem); return ret; } -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index ee89ecc2..84d21a9a 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -3,17 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" -- cgit v1.2.2 From 0d63e22a9920eb1e3d8653665cda650eca2311cd Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 27 Sep 2017 11:18:13 -0700 Subject: gpu: nvgpu: gv11b: check for memory aperture type Check for memory aperture type before setting relevant sysmem non-coherent or vidmem flags in ram entry. Modified following functions to correct memory aperture type: gv11b_get_ch_runlist_entry gv11b_subctx_commit_pdb Added following hw constants for chan_inst_target: ram_rl_entry_chan_inst_target_sys_mem_coh_v ram_rl_entry_chan_inst_target_vid_mem_v Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1569521 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 84d21a9a..4951d3a4 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -158,12 +158,15 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, u32 format_word; u32 pdb_addr_lo, pdb_addr_hi; u64 pdb_addr; + u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem, + ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), + ram_in_sc_page_dir_base_target_vid_mem_v()); pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( - ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | + aperture, 0) | ram_in_sc_page_dir_base_vol_f( ram_in_sc_page_dir_base_vol_true_v(), 0) | ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) | -- cgit v1.2.2 From 075852f042b9b3a3d48180378e6d2a709708cc41 Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 6 Nov 2017 13:44:44 +0200 Subject: gpu: nvgpu: Switch to newer NVGPU_AS_MAP_BUFFER flags Switch two cases using the old NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_* flags to the newer definitions, that is, NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE. The legacy NVGPU_MAP_BUFFER_FLAGS_* definitions have been deleted. Bug 1902982 Change-Id: Ifbd2678b10005b4af2375600888469b01dd09f4e Signed-off-by: Sami Kiminki Reviewed-on: https://git-master.nvidia.com/r/1592655 Reviewed-by: Alex Waterman Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 4951d3a4..864e24f0 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -75,7 +75,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, &ctx->mem, ctx->mem.size, - NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_FALSE, + 0, /* not GPU-cacheable */ gk20a_mem_flag_none, true, ctx->mem.aperture); if (!ctx->mem.gpu_va) { -- cgit v1.2.2 From 77a90d0b8d2eb1bbb207ae5f46b357f2d7cd07ab Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 14 Nov 2017 14:57:25 -0800 Subject: gpu: nvgpu: gv11b: modify dma alloc flags Call nvgpu_dma_alloc_flags_sys without NVGPU_DMA_NO_KERNEL_MAPPING flags, since it makes CMA memory handling simple in t194 and fixes error during subcontext header free: [ 340.378910] trying to free invalid coherent area: ffffffc0135ba000^M [ 340.378921] ------------[ cut here ]------------^M [ 340.378933] WARNING: CPU: 0 PID: 1618 at /code/volta/kernel/kernel-4.9/arch/arm64/mm/dma-mapping.c:1442 __arm_dma_free.isra.4+0x160/0x168^M [ 340.378950] Modules linked in: nvgpu^M [ 340.378958] ^M [ 340.378966] CPU: 0 PID: 1618 Comm: nvogtest Tainted: G W 4.9.52-tegra-g170e0c4 #20^M [ 340.378979] Hardware name: t194pre_si (DT)^M [ 340.378988] task: ffffffc018930d80 task.stack: ffffffc017e08000^M [ 340.378999] PC is at __arm_dma_free.isra.4+0x160/0x168^M [ 340.379009] LR is at __arm_dma_free.isra.4+0x160/0x168^M [ 340.379020] pc : [] lr : [] pstate: 60400045^M [ 340.379032] sp : ffffffc017e0bbe0^M [ 340.379039] x29: ffffffc017e0bbe0 x28: 00000000935ba000 ^M [ 340.379051] x27: 0000000000001000 x26: ffffffc0135b9580 ^M [ 340.379063] x25: ffffff8009ced1b0 x24: 0000000000000010 ^M [ 340.379075] x23: ffffffc070746010 x22: 0000000080000000 ^M [ 340.379088] x21: ffffffbf004d6e80 x20: ffffffc0135ba000 ^M [ 340.379100] x19: 0000000000001000 x18: ffffffffffffffff ^M [ 340.379112] x17: 0000007fa4d8fc60 x16: ffffff800823e370 ^M [ 340.379124] x15: ffffff8009cd8690 x14: ffffff8089fb34bf ^M [ 340.379135] x13: ffffff8009fb34cd x12: 0000000000000007 ^M [ 340.379147] x11: 0000000000000325 x10: 0000000005f5e0ff ^M [ 340.379159] x9 : 0000000000000326 x8 : 3331306366666666 ^M [ 340.379172] x7 : 6666203a61657261 x6 : ffffff8009fb3505 ^M [ 340.379184] x5 : 0000000000000012 x4 : 0000000000000000 ^M [ 340.379196] x3 : 0000000000010000 x2 : 0000000000040934 ^M [ 340.379207] x1 : 0000000000000000 x0 : 0000000000000036 ^M [ 340.379219] ^M [ 340.379224] ---[ end trace 9e7ab41f55eb32d2 ]---^M [ 340.379232] Call trace:^M [ 340.379241] [] __arm_dma_free.isra.4+0x160/0x168^M [ 340.379254] [] arm_dma_free+0x48/0x60^M [ 340.379827] [] nvgpu_dma_free+0x260/0x410 [nvgpu]^M [ 340.380403] [] gv11b_free_subctx_header+0x5c/0x80 [nvgpu]^M [ 340.380980] [] gk20a_free_channel_ctx+0x3c/0x150 [nvgpu]^M After changing dma alloc flags to none, this issue got fixed. Bug 1930032 Change-Id: I002236373c6a3ae5d7ec80a35f166429821662b7 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1598193 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 864e24f0..fe1aa8a5 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -65,7 +65,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (ctx->mem.gpu_va == 0) { ret = nvgpu_dma_alloc_flags_sys(g, - NVGPU_DMA_NO_KERNEL_MAPPING, + 0, /* No Special flags */ ctxsw_prog_fecs_header_v(), &ctx->mem); if (ret) { -- cgit v1.2.2