From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/pmu_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c new file mode 100644 index 00000000..0b0144ce --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -0,0 +1,27 @@ +/* + * GV11B PMU + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for udelay */ +#include +#include "gk20a/gk20a.h" +#include "gp10b/pmu_gp10b.h" + +#include "pmu_gv11b.h" +#include "hw_pwr_gv11b.h" + +void gv11b_init_pmu_ops(struct gpu_ops *gops) +{ + gp10b_init_pmu_ops(gops); +} -- cgit v1.2.2 From 56fcce12e00187438529d44f2e70cd28df9288bc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 27 Oct 2016 11:16:30 -0700 Subject: gpu: nvgpu: gv11b: pmu HAL update Update pmu HAL to have function for is_pmu_supported(). At this moment pmu support is disabled for gv11b. JIRA GV11B-21 Change-Id: I1790e6e4dc80e0761df78e6092da2b6ca0e39d64 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1243919 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 0b0144ce..62e42c31 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -21,7 +21,13 @@ #include "pmu_gv11b.h" #include "hw_pwr_gv11b.h" +static bool gv11b_is_pmu_supported(struct gk20a *g) +{ + return false; +} + void gv11b_init_pmu_ops(struct gpu_ops *gops) { gp10b_init_pmu_ops(gops); + gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; } -- cgit v1.2.2 From ea1330f2ede5302301af95ff4af7ff49f87fd3e5 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 24 Nov 2016 09:46:13 +0530 Subject: nvgpu: gv11b: Add non secure PMU bootstrap(). pmu_bootstrap() does not support gv11b PMU non-secure boot. gv11b_pmu_bootstrap function is added with the updated/new args. JIRA GV11B-30 Change-Id: I42c1a7bd77d75c6e59ee4cc695cc879ce7cec095 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1259271 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 121 +++++++++++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 62e42c31..e235e39b 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B PMU * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,19 +15,138 @@ #include /* for udelay */ #include +#include #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" #include "pmu_gv11b.h" #include "hw_pwr_gv11b.h" +#define ALIGN_4KB 12 + static bool gv11b_is_pmu_supported(struct gk20a *g) { return false; } +static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) +{ + struct gk20a *g = gk20a_from_pmu(pmu); + struct gk20a_platform *platform = dev_get_drvdata(g->dev); + struct mm_gk20a *mm = &g->mm; + struct pmu_ucode_desc *desc = pmu->desc; + u64 addr_code_lo, addr_data_lo, addr_load_lo; + u64 addr_code_hi, addr_data_hi, addr_load_hi; + u32 i, blocks, addr_args; + + gk20a_dbg_fn(""); + + gk20a_writel(g, pwr_falcon_itfen_r(), + gk20a_readl(g, pwr_falcon_itfen_r()) | + pwr_falcon_itfen_ctxen_enable_f()); + + gk20a_writel(g, pwr_pmu_new_instblk_r(), + pwr_pmu_new_instblk_ptr_f( + gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) + | pwr_pmu_new_instblk_valid_f(1) + | pwr_pmu_new_instblk_target_sys_ncoh_f()); + + /* TBD: load all other surfaces */ + g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( + pmu, GK20A_PMU_TRACE_BUFSIZE); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( + pmu, GK20A_PMU_DMAIDX_VIRT); + + g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, + clk_get_rate(platform->clk[1])); + + addr_args = (pwr_falcon_hwcfg_dmem_size_v( + gk20a_readl(g, pwr_falcon_hwcfg_r())) + << GK20A_PMU_DMEM_BLKSIZE2) - + g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); + + pmu_copy_to_dmem(pmu, addr_args, + (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), + g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); + + gk20a_writel(g, pwr_falcon_dmemc_r(0), + pwr_falcon_dmemc_offs_f(0) | + pwr_falcon_dmemc_blk_f(0) | + pwr_falcon_dmemc_aincw_f(1)); + + addr_code_lo = u64_lo32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_code_offset) >> 8); + + addr_code_hi = u64_hi32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_code_offset) >> 8); + addr_data_lo = u64_lo32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_data_offset) >> 8); + addr_data_hi = u64_hi32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_data_offset) >> 8); + addr_load_lo = u64_lo32((pmu->ucode.gpu_va + + desc->bootloader_start_offset) >> 8); + addr_load_hi = u64_hi32((pmu->ucode.gpu_va + + desc->bootloader_start_offset) >> 8); + + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), GK20A_PMU_DMAIDX_UCODE); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_code_lo << 8); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_code_hi); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_code_offset); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_code_size); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_imem_entry); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_data_lo << 8); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_data_hi); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_data_size); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x1); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_args); + + g->ops.pmu.write_dmatrfbase(g, + addr_load_lo - (desc->bootloader_imem_offset >> 8)); + + blocks = ((desc->bootloader_size + 0xFF) & ~0xFF) >> 8; + + for (i = 0; i < blocks; i++) { + gk20a_writel(g, pwr_falcon_dmatrfmoffs_r(), + desc->bootloader_imem_offset + (i << 8)); + gk20a_writel(g, pwr_falcon_dmatrffboffs_r(), + desc->bootloader_imem_offset + (i << 8)); + gk20a_writel(g, pwr_falcon_dmatrfcmd_r(), + pwr_falcon_dmatrfcmd_imem_f(1) | + pwr_falcon_dmatrfcmd_write_f(0) | + pwr_falcon_dmatrfcmd_size_f(6) | + pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); + } + + gk20a_writel(g, pwr_falcon_bootvec_r(), + pwr_falcon_bootvec_vec_f(desc->bootloader_entry_point)); + + gk20a_writel(g, pwr_falcon_cpuctl_r(), + pwr_falcon_cpuctl_startcpu_f(1)); + + gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); + + return 0; +} + + void gv11b_init_pmu_ops(struct gpu_ops *gops) { gp10b_init_pmu_ops(gops); + gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; } -- cgit v1.2.2 From 3a4a7d196a6a7fd256052cded45d6763c20dd3f6 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 18 Jan 2017 18:32:09 +0530 Subject: drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse header The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Ied87164ea1de793d97a4cc6a754150164af04698 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/1287500 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index e235e39b..9ee1ed30 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -14,8 +14,8 @@ */ #include /* for udelay */ -#include #include +#include #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 9ee1ed30..6b56dd21 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -15,12 +15,16 @@ #include /* for udelay */ #include + #include + #include "gk20a/gk20a.h" + #include "gp10b/pmu_gp10b.h" #include "pmu_gv11b.h" -#include "hw_pwr_gv11b.h" + +#include #define ALIGN_4KB 12 -- cgit v1.2.2 From cabba6686643dbb4bd8a023ad4622a49114b5159 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 16 Jan 2017 10:55:22 +0530 Subject: nvgpu: pmu: Assign pmu_queue_get_head/tail ops. pmu_get_queue_head/tail & pmu_get_queue_head/tail_size ops are defined for gv11b chip. JIRA GV11B-30 Change-Id: Iae139732d9f68f93e3c197469c04ccd3f0d63ce7 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1285749 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 6b56dd21..8432bd20 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -153,4 +153,8 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gp10b_init_pmu_ops(gops); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; + gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; + gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; + gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; + gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; } -- cgit v1.2.2 From 53e718a739b4c6d6e3a1f4993a4722f28a40cff3 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 13 Feb 2017 15:13:12 +0530 Subject: gpu: nvgpu: gv11b: Use secure PMU reset for GV11B. PMU reset for GV11B is PRIV protected. gp106_pmu_reset() also uses the same register to reset PMU, therefore used same function for gv11b. Change-Id: I633a96256598e73ed02cbdfe0afdb9fba8b76afd Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1303740 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 8432bd20..29ef7f6c 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" +#include "gp106/pmu_gp106.h" #include "pmu_gv11b.h" @@ -153,6 +154,7 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gp10b_init_pmu_ops(gops); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; + gops->pmu.reset = gp106_pmu_reset; gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; -- cgit v1.2.2 From fbce374aa0f6101d27ca5b3de97905d2798c6f04 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 6 Apr 2017 12:08:08 +0530 Subject: gpu: nvgpu: Enable PMU support for T19X. JIRA GPUT19X-30 Change-Id: Ib9cb19eb1850c70f3e6db60660184569f5165263 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1253565 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 29ef7f6c..4cc45197 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -31,7 +31,7 @@ static bool gv11b_is_pmu_supported(struct gk20a *g) { - return false; + return true; } static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) -- cgit v1.2.2 From e1c27d4e84d518bef88305d1ca848deb07433677 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:15:50 -0700 Subject: gpu: nvgpu: gv11b: Use new clk HAL Use the new clk HAL to request clock rate instead of direct calls to Clock Framework. This cuts one direct dependency to Linux APIs. Also change the HAL to not clear clk ops after they've been initialized. JIRA NVGPU-16 Change-Id: I1ab3eac8268f1f3f3305d49782c6a0eb57c6d617 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463536 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 4cc45197..4784ee4a 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -37,7 +37,6 @@ static bool gv11b_is_pmu_supported(struct gk20a *g) static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); - struct gk20a_platform *platform = dev_get_drvdata(g->dev); struct mm_gk20a *mm = &g->mm; struct pmu_ucode_desc *desc = pmu->desc; u64 addr_code_lo, addr_data_lo, addr_load_lo; @@ -64,7 +63,7 @@ static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) pmu, GK20A_PMU_DMAIDX_VIRT); g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, - clk_get_rate(platform->clk[1])); + g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); addr_args = (pwr_falcon_hwcfg_dmem_size_v( gk20a_readl(g, pwr_falcon_hwcfg_r())) -- cgit v1.2.2 From df03ec9e3064b027fe5459675f445fb591ef96ee Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 12 May 2017 17:39:57 +0530 Subject: gpu: nvgpu: pmu: Re-use elpg stats function. Assign gp106_pmu_elpg_statistics() for pmu elpg stats in gv11b. Bug 200305607 Change-Id: I18b2b4b7a527d692894e190871db0909bec5aebc Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1480844 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 4784ee4a..50ddb07b 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -158,4 +158,5 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; + gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; } -- cgit v1.2.2 From 16a9ec4a12654b04a3db82de25cf6471389e4693 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 10 May 2017 23:03:28 +0530 Subject: gpu: nvgpu: renamed "struct pmu_gk20a" to "struct nvgpu_pmu" JIRA NVGPU-56 Change-Id: I73a375cf2f3d544357fb390491a8d70d12fb8562 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1479299 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 50ddb07b..35246138 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -34,7 +34,7 @@ static bool gv11b_is_pmu_supported(struct gk20a *g) return true; } -static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) +static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); struct mm_gk20a *mm = &g->mm; -- cgit v1.2.2 From 002d6f147490cd5b3002ce5a564f4276df784ea6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 10 May 2017 17:18:01 +0530 Subject: gpu: nvgpu: PMU IPC reorg support update - prepend PMU IPC func with nvgpu_ by replacing gk20a_ - updated gv11b HAL methods of queue & mutex to point to gk20a HAL methods. JIRA NVGPU-56 Change-Id: Iade9f5613dbd4bc11515e822ddfda3a1787bfa4f Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1479117 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 35246138..4c2b6dca 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -158,5 +158,9 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; + gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; + gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; + gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; + gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; } -- cgit v1.2.2 From 263cb402293d2050d7d08212e89e4c1dcb1d4ccc Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sat, 10 Jun 2017 11:38:23 +0530 Subject: gpu: nvgpu: PMU init reorg support update -Updated gv11b HAL, pmu_msgq_tail & pmu_mutex_size to point to gk20a_pmu_msgq_tail() & pwr_pmu_mutex__size_1_v() JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: I8fe271f778fc2d70360f8a508f36d0bfce6b341d Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1499701 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 4c2b6dca..2376e66e 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -162,5 +162,7 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; + gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; + gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; } -- cgit v1.2.2 From 3afd4af3a73b17317021f3dbca02dbc806a0fc5f Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Fri, 26 May 2017 11:43:36 +0530 Subject: nvgpu: nvgpu: gv11b: Add/Update PMU cmds for ELPG. This patch: - Adds a PMU command needed for enabling ELPG. i.e. command to update sub-feature mask to enable ELPG. - Adds a new version of PG-GR init param command function which uses updated command interface. JIRA GPUT19X-20. Change-Id: If969c018e2e28264fdc9c897892eb28b021d12f2 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1504873 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 89 +++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 2376e66e..ef4a715d 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -27,6 +27,9 @@ #include +#define gv11b_dbg_pmu(fmt, arg...) \ + gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) + #define ALIGN_4KB 12 static bool gv11b_is_pmu_supported(struct gk20a *g) @@ -147,6 +150,90 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) return 0; } +static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + gk20a_dbg_fn(""); + + if (status != 0) { + nvgpu_err(g, "Sub-feature mask update cmd aborted\n"); + return; + } + + gv11b_dbg_pmu("sub-feature mask update is acknowledged from PMU %x\n", + msg->msg.pg.msg_type); +} + +static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + gk20a_dbg_fn(""); + + if (status != 0) { + nvgpu_err(g, "GR PARAM cmd aborted\n"); + return; + } + + gv11b_dbg_pmu("GR PARAM is acknowledged from PMU %x\n", + msg->msg.pg.msg_type); +} + +static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_gr_init_param_v1); + cmd.cmd.pg.gr_init_param_v1.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.gr_init_param_v1.sub_cmd_id = + PMU_PG_PARAM_CMD_GR_INIT_PARAM; + cmd.cmd.pg.gr_init_param_v1.featuremask = + PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + + gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_pg_param_msg, pmu, &seq, ~0); + + } else + return -EINVAL; + + return 0; +} + +static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_sub_feature_mask_update); + cmd.cmd.pg.sf_mask_update.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.sf_mask_update.sub_cmd_id = + PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE; + cmd.cmd.pg.sf_mask_update.ctrl_id = + PMU_PG_ELPG_ENGINE_ID_GRAPHICS; + cmd.cmd.pg.sf_mask_update.enabled_mask = + PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + + gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); + } else + return -EINVAL; + + return 0; +} void gv11b_init_pmu_ops(struct gpu_ops *gops) { @@ -165,4 +252,6 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; + gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; + gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; } -- cgit v1.2.2 From 5107bda90a1e55d4850a8f1c27008f05c420b4ec Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 21 Jun 2017 23:36:59 +0530 Subject: gpu: nvgpu: gv11b, use nvgpu_flcn_copy_to_dmem() - replace usage of pmu_copy_to_dmem() with nvgpu_flcn_copy_to_dmem() JIRA NVGPU-99 Change-Id: I8d0ce1cb7adffc4df57044b8887d525c1f2f0237 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1506582 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index ef4a715d..01dc207c 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -73,7 +73,7 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) << GK20A_PMU_DMEM_BLKSIZE2) - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); - pmu_copy_to_dmem(pmu, addr_args, + nvgpu_flcn_copy_to_dmem(pmu->flcn, addr_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); -- cgit v1.2.2 From dedc347b94123f0e049f6845990cb41c679cbdeb Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 23 Jun 2017 17:22:48 +0530 Subject: gpu: nvgpu: PMU reset reorg support - Assigned gv11b pmu engine reset & status ops to point to gp106 ops. JIRA NVGPU-99 Change-Id: I6338e2c5a1458e88a62cf0966b59c1dbe73385b6 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1507884 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 01dc207c..ecc77e1b 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -240,7 +240,8 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gp10b_init_pmu_ops(gops); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; - gops->pmu.reset = gp106_pmu_reset; + gops->pmu.reset_engine = gp106_pmu_engine_reset; + gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset; gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; -- cgit v1.2.2 From f9c4f8b443c5394eb3ae5027c483d57ab0c5d515 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 4 Jul 2017 13:06:38 +0530 Subject: gpu: nvgpu: gv11b, rename gk20a_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I1ce20cdd7190311535917058ad09a8896e505179 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1512972 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index ecc77e1b..fe468f19 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -197,7 +197,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_param_msg, pmu, &seq, ~0); } else @@ -227,7 +227,7 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); } else return -EINVAL; -- cgit v1.2.2 From ce308666f55cd4699c9e118cac291879ddc066ed Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 5 Jul 2017 16:25:35 +0530 Subject: gpu: nvgpu: gv11b, use nvgpu_flcn_bootstrap() - Replaced falcon bootstrap code with nvgpu_flcn_bootstrap() method JIRA NVGPU-102 Change-Id: I5133419957c890847cac66c5ac018e8188db41e3 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1513647 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index fe468f19..d20b9c1a 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -18,6 +18,9 @@ #include +#include +#include + #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" @@ -139,11 +142,7 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); } - gk20a_writel(g, pwr_falcon_bootvec_r(), - pwr_falcon_bootvec_vec_f(desc->bootloader_entry_point)); - - gk20a_writel(g, pwr_falcon_cpuctl_r(), - pwr_falcon_cpuctl_startcpu_f(1)); + nvgpu_flcn_bootstrap(pmu->flcn, desc->bootloader_entry_point); gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); -- cgit v1.2.2 From 2b98e1308d49b9c941d8fa6fc87f67108d6d9370 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 24 Jul 2017 12:19:53 -0700 Subject: gpu: nvgpu: gv11b: Remove privsecurity from gpu_ops Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1525714 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index d20b9c1a..35719dff 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -20,6 +20,7 @@ #include #include +#include #include "gk20a/gk20a.h" @@ -234,9 +235,11 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } -void gv11b_init_pmu_ops(struct gpu_ops *gops) +void gv11b_init_pmu_ops(struct gk20a *g) { - gp10b_init_pmu_ops(gops); + struct gpu_ops *gops = &g->ops; + + gp10b_init_pmu_ops(g); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; gops->pmu.reset_engine = gp106_pmu_engine_reset; -- cgit v1.2.2 From cce0a55d2106865be14b3b39c083a0f55881f2a5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 1 Aug 2017 17:12:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg pmu HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 32 ++++---------------------------- 1 file changed, 4 insertions(+), 28 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 35719dff..2b89fbcc 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -36,12 +36,12 @@ #define ALIGN_4KB 12 -static bool gv11b_is_pmu_supported(struct gk20a *g) +bool gv11b_is_pmu_supported(struct gk20a *g) { return true; } -static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) +int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); struct mm_gk20a *mm = &g->mm; @@ -178,7 +178,7 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, msg->msg.pg.msg_type); } -static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) +int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; @@ -206,7 +206,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) return 0; } -static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) +int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; @@ -234,27 +234,3 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } - -void gv11b_init_pmu_ops(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - gp10b_init_pmu_ops(g); - gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; - gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; - gops->pmu.reset_engine = gp106_pmu_engine_reset; - gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset; - gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; - gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; - gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; - gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; - gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; - gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; - gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; - gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; - gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; - gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; - gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; - gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; - gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; -} -- cgit v1.2.2 From c094ea161785a8c00bb2dc8c55e1a2bb8ffbcfc7 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 30 Aug 2017 15:03:25 +0530 Subject: gpu: nvgpu: gv11b: Secure boot support. This patch adds Secure boot support for T194. JIRA GPUT19X-5 Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1514558 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 2b89fbcc..41c6199e 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -28,6 +28,7 @@ #include "gp106/pmu_gp106.h" #include "pmu_gv11b.h" +#include "acr_gv11b.h" #include @@ -41,6 +42,42 @@ bool gv11b_is_pmu_supported(struct gk20a *g) return true; } +bool gv11b_is_lazy_bootstrap(u32 falcon_id) +{ + bool enable_status = false; + + switch (falcon_id) { + case LSF_FALCON_ID_FECS: + enable_status = true; + break; + case LSF_FALCON_ID_GPCCS: + enable_status = true; + break; + default: + break; + } + + return enable_status; +} + +bool gv11b_is_priv_load(u32 falcon_id) +{ + bool enable_status = false; + + switch (falcon_id) { + case LSF_FALCON_ID_FECS: + enable_status = true; + break; + case LSF_FALCON_ID_GPCCS: + enable_status = true; + break; + default: + break; + } + + return enable_status; +} + int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 41c6199e..74ed9165 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include /* for udelay */ -- cgit v1.2.2 From 0899e11d4bb630381607a0c245f72476e2e9209e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 6 Oct 2017 17:20:12 -0700 Subject: gpu: nvgpu: Cleanup generic MM code t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 74ed9165..2c7b6457 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" @@ -104,7 +105,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) gk20a_writel(g, pwr_pmu_new_instblk_r(), pwr_pmu_new_instblk_ptr_f( - gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) + nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) | pwr_pmu_new_instblk_valid_f(1) | pwr_pmu_new_instblk_target_sys_ncoh_f()); -- cgit v1.2.2