From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/mm_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c new file mode 100644 index 00000000..0ac18a91 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -0,0 +1,25 @@ +/* + * GV11B MMU + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include "gk20a/gk20a.h" +#include "gp10b/mm_gp10b.h" +#include "mm_gv11b.h" + +void gv11b_init_mm(struct gpu_ops *gops) +{ + gp10b_init_mm(gops); +} -- cgit v1.2.2 From 1a36091fb9e31578c2e01c60cbe0a9b01b64bc9e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Sat, 24 Sep 2016 11:20:37 -0700 Subject: gpu: nvgpu: gv11b: sysmem userd support For gv11b, userd is allocated from sysmem. Updated gp_get and gp_put functions to read or write from sysmem instead of bar1 memory. In gv11b, after updating gp_put, it is required to notify pending work to host through channel doorbell. JIRA GV11B-1 Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1226613 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 0ac18a91..54df6745 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -18,8 +18,16 @@ #include "gk20a/gk20a.h" #include "gp10b/mm_gp10b.h" #include "mm_gv11b.h" +#include "hw_fb_gv11b.h" + +bool gv11b_mm_is_bar1_supported(struct gk20a *g) +{ + return false; +} void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); + gops->mm.bar1_bind = NULL; + gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; } -- cgit v1.2.2 From 2de62a6083075451318c2ef6b5323f50bf5ebc3f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 14 Oct 2016 05:05:16 -0700 Subject: gpu: nvgpu: gv11b: fix sparse warning Fix following sparse warning my making funtion as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:23:6: warning: symbol 'gv11b_mm_is_bar1_supported' was not declared. Should it be static? Bug 200088648 Change-Id: I4af7ed1ae112813887a14a11b8fcea0b72c90e39 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1236689 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 54df6745..80ac21e6 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -20,7 +20,7 @@ #include "mm_gv11b.h" #include "hw_fb_gv11b.h" -bool gv11b_mm_is_bar1_supported(struct gk20a *g) +static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -- cgit v1.2.2 From 1eb564a27946305e164269a4f6e2005aa797f7e5 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 10:43:29 -0800 Subject: gpu: nvgpu: gv11b: chip specific init_inst_block Remove va limits for inst block in gv11b. JIRA GV11B-21 Change-Id: I5338e2d64b3bbebeb5e309d63db3e8360ae05723 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254880 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 80ac21e6..ff4e3b06 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -25,9 +25,25 @@ static bool gv11b_mm_is_bar1_supported(struct gk20a *g) return false; } +static void gv11b_init_inst_block(struct mem_desc *inst_block, + struct vm_gk20a *vm, u32 big_page_size) +{ + struct gk20a *g = gk20a_from_vm(vm); + + gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", + gk20a_mm_inst_block_addr(g, inst_block), inst_block->cpu_va); + + g->ops.mm.init_pdb(g, inst_block, vm); + + if (big_page_size && g->ops.mm.set_big_page_size) + g->ops.mm.set_big_page_size(g, inst_block, big_page_size); +} + + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); gops->mm.bar1_bind = NULL; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; + gops->mm.init_inst_block = gv11b_init_inst_block; } -- cgit v1.2.2 From 331762a7e78924296dacb4c1465e67679d4b57f7 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 22 Nov 2016 10:31:42 -0800 Subject: gpu: nvgpu: gv11b: implement mm_setup_hw Reuse gk20a_mm_setup_hw for gv11b. JIRA GV11B-21 Change-Id: I5141dbb8088799a8bd5df55469bc371b63497e96 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254939 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index ff4e3b06..7f104a6d 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -46,4 +46,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.bar1_bind = NULL; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; + gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; } -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7f104a6d..404ee921 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B MMU * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,10 +15,14 @@ #include #include + #include "gk20a/gk20a.h" + #include "gp10b/mm_gp10b.h" + #include "mm_gv11b.h" -#include "hw_fb_gv11b.h" + +#include static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { -- cgit v1.2.2 From e83372e0cc78a16777f0d2f43936e772f40308d2 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Tue, 14 Mar 2017 13:37:58 +0200 Subject: gpu: nvgpu: gv11b: abstract away dma alloc attrs Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct mem_desc now. Bug 1853519 Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1321314 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 404ee921..d49c3b73 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -14,7 +14,6 @@ */ #include -#include #include "gk20a/gk20a.h" -- cgit v1.2.2 From e24ed1f6d77dc8b277a1b4735228c5c0011559d4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 3 Mar 2017 13:51:07 -0800 Subject: gpu: nvgpu: gv11b: init mm ops for mmu_fault_pending mmu fault reporting is moved from fifo* to fb* and gmmu* hw registers. JIRA GPUT19X-7 Change-Id: If2040ab661229c2e734042f2eec1592030615fee Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1315203 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index d49c3b73..fd77ed10 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -42,6 +42,15 @@ static void gv11b_init_inst_block(struct mem_desc *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } +static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +{ + if (gk20a_readl(g, fb_niso_intr_r()) & + (fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() | + fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f())) + return true; + + return false; +} void gv11b_init_mm(struct gpu_ops *gops) { @@ -50,4 +59,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; + gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; } -- cgit v1.2.2 From d409d7ebc136470906b861f3bebb7da63e1557e6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 17 Mar 2017 13:47:54 -0700 Subject: gpu: nvgpu: Add bus HAL Add bus HAL and separate bus related functions from mm_gv11b: timer access. Change-Id: I311f258857238233103688fb653d27e4e79005a4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1323354 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index fd77ed10..84a9449a 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -55,7 +55,6 @@ static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); - gops->mm.bar1_bind = NULL; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; -- cgit v1.2.2 From c876bec8bab5a1e4d6dea529700ef19c5eac5e64 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:01:14 -0700 Subject: gpu: nvgpu: rename mem_desc to nvgpu_mem $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 84a9449a..269108ff 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -28,7 +28,7 @@ static bool gv11b_mm_is_bar1_supported(struct gk20a *g) return false; } -static void gv11b_init_inst_block(struct mem_desc *inst_block, +static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); -- cgit v1.2.2 From 47eed280133ee75327942539c6d07e9b89d237f4 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 15 Jun 2017 16:07:05 -0700 Subject: gpu: nvgpu: gv11b: fb_flush before/after l2_flush After enabling l2 write back in gv11b, for committing all dirty data to sysmem correctly: Added one fb_flush before l2_flush to commit dirty hshub data to l2/sysmem. Added one more fb_flush after l2_flush, to commit any new dirty data on hshub to sysmem. This done by implementing gv11b specific l2_flush function. Bug 1937331 Change-Id: Ie30edb12c98c4021783c88750bb4c4ca62e4a7ca Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1503385 Reviewed-by: Alex Waterman Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 269108ff..9d1e0f25 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -52,6 +52,15 @@ static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) return false; } +void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) +{ + nvgpu_log(g, gpu_dbg_fn, "gv11b_mm_l2_flush"); + + g->ops.mm.fb_flush(g); + gk20a_mm_l2_flush(g, invalidate); + g->ops.mm.fb_flush(g); +} + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); @@ -59,4 +68,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; + gops->mm.l2_flush = gv11b_mm_l2_flush; } -- cgit v1.2.2 From afa31cdd8cc6bb04faeed30b2cc30f5e6be888b5 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 3 Jul 2017 16:40:44 +0530 Subject: gpu: nvgpu: add support for L3 cache allocation of buffers Add gv11b implementation of gpu_phys_addr() that checks the t19x GMMU attributes struct to determine if L3 allocation should be enabled. If L3 alloc is enabled then a special physical address bit is set. Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct nvgpu_as_map_buffer_ex_args so that User space can add a hint to allocate buffer in L3 cache Jira GPUT19X-10 Bug 200279508 Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master/r/1512602 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 9d1e0f25..cc8dafa3 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -23,6 +23,8 @@ #include +#define NVGPU_L3_ALLOC_BIT 36 + static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; @@ -61,6 +63,20 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) g->ops.mm.fb_flush(g); } +/* + * On Volta the GPU determines whether to do L3 allocation for a mapping by + * checking bit 36 of the phsyical address. So if a mapping should allocte lines + * in the L3 this bit must be set. + */ +u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys) +{ + if (attrs->t19x_attrs.l3_alloc) + return phys | NVGPU_L3_ALLOC_BIT; + + return phys; +} + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); @@ -69,4 +85,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; gops->mm.l2_flush = gv11b_mm_l2_flush; + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; } -- cgit v1.2.2 From aa05648fd6038b69d1ed841f33b24cf1875efd83 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 2 Jun 2017 09:58:23 -0700 Subject: gpu: nvgpu: gv11b: set up for enabling/handling hub intr -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 198 +++++++++++++++++++++++++++++++++++-- 1 file changed, 192 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index cc8dafa3..d6184cee 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -15,13 +15,21 @@ #include +#include +#include +#include + #include "gk20a/gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "mm_gv11b.h" +#include "fb_gv11b.h" #include +#include #define NVGPU_L3_ALLOC_BIT 36 @@ -46,12 +54,187 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { - if (gk20a_readl(g, fb_niso_intr_r()) & - (fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() | - fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f())) - return true; + return gv11b_fb_mmu_fault_pending(g); +} - return false; +static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +{ + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); + + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER | + HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); + + nvgpu_kfree(g, g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]); + + g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY] = NULL; + g->mm.fault_info[FAULT_TYPE_REPLAY] = NULL; + + nvgpu_mutex_release(&g->mm.hub_isr_mutex); + nvgpu_mutex_destroy(&g->mm.hub_isr_mutex); +} + +static int gv11b_mm_mmu_fault_info_buf_init(struct gk20a *g, + u32 *hub_intr_types) +{ + struct mmu_fault_info *fault_info_mem; + + fault_info_mem = nvgpu_kzalloc(g, sizeof(struct mmu_fault_info) * + FAULT_TYPE_NUM); + if (!fault_info_mem) { + nvgpu_log_info(g, "failed to alloc shadow fault info"); + return -ENOMEM; + } + /* shadow buffer for copying mmu fault info */ + g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY] = + &fault_info_mem[FAULT_TYPE_OTHER_AND_NONREPLAY]; + + g->mm.fault_info[FAULT_TYPE_REPLAY] = + &fault_info_mem[FAULT_TYPE_REPLAY]; + + *hub_intr_types |= HUB_INTR_TYPE_OTHER; + return 0; +} + +static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, + u32 *hub_intr_types) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + int err = 0; + size_t fb_size; + + /* Max entries take care of 1 entry used for full detection */ + fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * + gmmu_fault_buf_size_v(); + + err = nvgpu_dma_alloc_map_sys(vm, fb_size, + &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + if (err) { + nvgpu_err(g, + "Error in hw mmu fault buf [0] alloc in bar2 vm "); + /* Fault will be snapped in pri reg but not in buffer */ + return; + } + + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_TRUE; + *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; + + err = nvgpu_dma_alloc_map_sys(vm, fb_size, + &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + if (err) { + nvgpu_err(g, + "Error in hw mmu fault buf [1] alloc in bar2 vm "); + /* Fault will be snapped in pri reg but not in buffer */ + return; + } + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_TRUE; + *hub_intr_types |= HUB_INTR_TYPE_REPLAY; +} + +static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY | + HUB_INTR_TYPE_REPLAY); + + g->mm.hub_intr_types &= (~(HUB_INTR_TYPE_NONREPLAY | + HUB_INTR_TYPE_REPLAY)); + + if ((gv11b_fb_is_fault_buf_enabled(g, NONREPLAY_REG_INDEX))) { + gv11b_fb_fault_buf_set_state_hw(g, NONREPLAY_REG_INDEX, + FAULT_BUF_DISABLED); + } + + if ((gv11b_fb_is_fault_buf_enabled(g, REPLAY_REG_INDEX))) { + gv11b_fb_fault_buf_set_state_hw(g, REPLAY_REG_INDEX, + FAULT_BUF_DISABLED); + } + + if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + nvgpu_dma_unmap_free(vm, + &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + } + + if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + nvgpu_dma_unmap_free(vm, + &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + } +} + +static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + + gv11b_mm_mmu_hw_fault_buf_deinit(g); + + gk20a_free_inst_block(g, &mm->bar2.inst_block); + nvgpu_vm_put(mm->bar2.vm); +} + +static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g) +{ + if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX); + } + if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX); + } +} + +static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) +{ + int err; + + nvgpu_mutex_init(&g->mm.hub_isr_mutex); + + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + + g->mm.hub_intr_types = HUB_INTR_TYPE_ECC_UNCORRECTED; + + err = gv11b_mm_mmu_fault_info_buf_init(g, &g->mm.hub_intr_types); + + if (!err) + gv11b_mm_mmu_hw_fault_buf_init(g, &g->mm.hub_intr_types); + + return err; +} + +static int gv11b_init_mm_setup_hw(struct gk20a *g) +{ + int err = 0; + + nvgpu_log_fn(g, "start"); + + g->ops.fb.set_mmu_page_size(g); + g->ops.fb.init_hw(g); + + err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (err) + return err; + + if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) + return -EBUSY; + + err = gv11b_mm_mmu_fault_setup_sw(g); + if (!err) + gv11b_mm_mmu_fault_setup_hw(g); + + nvgpu_log_fn(g, "end"); + + return err; } void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) @@ -82,8 +265,11 @@ void gv11b_init_mm(struct gpu_ops *gops) gp10b_init_mm(gops); gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; gops->mm.l2_flush = gv11b_mm_l2_flush; gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; + gops->mm.fault_info_mem_destroy = + gv11b_mm_fault_info_mem_destroy; + gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; } -- cgit v1.2.2 From 2f6d321390a98ace1e52f21c6a399e06b3fe71e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Mar 2017 12:16:07 -0800 Subject: gpu: nvgpu: gv11b: add mmu fault handling HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index d6184cee..f4fc4db4 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -59,6 +59,8 @@ static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { + nvgpu_log_fn(g, " "); + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER | @@ -136,6 +138,8 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) { struct vm_gk20a *vm = g->mm.bar2.vm; + nvgpu_log_fn(g, " "); + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); @@ -173,6 +177,8 @@ static void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; + nvgpu_log_fn(g, " "); + gv11b_mm_mmu_hw_fault_buf_deinit(g); gk20a_free_inst_block(g, &mm->bar2.inst_block); @@ -195,6 +201,8 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) { int err; + nvgpu_log_fn(g, " "); + nvgpu_mutex_init(&g->mm.hub_isr_mutex); g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = @@ -216,7 +224,7 @@ static int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; - nvgpu_log_fn(g, "start"); + nvgpu_log_fn(g, " "); g->ops.fb.set_mmu_page_size(g); g->ops.fb.init_hw(g); -- cgit v1.2.2 From cdae0f137923b5996bf544eb676394e0e51e993f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sat, 8 Jul 2017 23:14:58 -0700 Subject: gpu: nvgpu: gv11b: check bar2 bind_status This is needed as BAR1 support is removed and there is no way to know if gpu successfully accessed memory. JIRA GPUT19X-115 Change-Id: I5d18b6bf73e11b103d1951d2e28fb1f895e72c85 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1515813 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index f4fc4db4..9430f576 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -30,6 +30,7 @@ #include #include +#include #define NVGPU_L3_ALLOC_BIT 36 @@ -268,6 +269,56 @@ u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } +static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct nvgpu_mem *inst_block = &mm->bar2.inst_block; + u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); + u32 reg_val; + struct nvgpu_timeout timeout; + u32 delay = GR_IDLE_CHECK_DEFAULT; + + nvgpu_log_fn(g, " "); + + g->ops.fb.set_mmu_page_size(g); + + inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); + nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); + + gk20a_writel(g, bus_bar2_block_r(), + nvgpu_aperture_mask(g, inst_block, + bus_bar2_block_target_sys_mem_ncoh_f(), + bus_bar2_block_target_vid_mem_f()) | + bus_bar2_block_mode_virtual_f() | + bus_bar2_block_ptr_f(inst_pa)); + + /* This is needed as BAR1 support is removed and there is no way + * to know if gpu successfully accessed memory. + * To avoid deadlocks and non-deterministic virtual address translation + * behavior, after writing BAR2_BLOCK to bind BAR2 to a virtual address + * space, SW must ensure that the bind has completed prior to issuing + * any further BAR2 requests by polling for both + * BUS_BIND_STATUS_BAR2_PENDING to return to EMPTY and + * BUS_BIND_STATUS_BAR2_OUTSTANDING to return to FALSE + */ + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + nvgpu_log_info(g, "check bar2 bind status"); + do { + reg_val = gk20a_readl(g, bus_bind_status_r()); + + if (!((reg_val & bus_bind_status_bar2_pending_busy_f()) || + (reg_val & bus_bind_status_bar2_outstanding_true_f()))) + return 0; + + nvgpu_usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, "bar2 bind timedout")); + + nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); + return -EBUSY; +} + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); @@ -280,4 +331,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy; gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; + gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; } -- cgit v1.2.2 From ea381959d973f013a2a2b2ae6fe694f1f569683c Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 31 Jul 2017 13:09:06 +0530 Subject: gpu: nvgpu: fix L3 alloc bit Last minute rebase of commit afa31cdd8cc6bb04faeed30b2cc30f5e6be888b5 on top of reworked memory infrastucture introduced a bug where we actually need to set BIT(36) in physical address but we ended up ORing the address by "36" Fix this by by adding correct value BIT(36) instead of 36 Jira GPUT19X-10 Bug 200279508 Change-Id: Ib587849c75f57dda5ad802b8389b7563b8b690ed Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1529511 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 9430f576..9be8352a 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -32,7 +32,7 @@ #include #include -#define NVGPU_L3_ALLOC_BIT 36 +#define NVGPU_L3_ALLOC_BIT BIT(36) static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { -- cgit v1.2.2 From 5a5792d911d99a08663c59f74c552883804780f3 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 8 Jun 2017 15:05:19 -0700 Subject: gpu: nvgpu: Remove mm.get_iova_addr Volta changes for equivalent change on nvgpu. JIRA NVGPU-30 Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1530863 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 9be8352a..7ba8f74f 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -260,10 +260,10 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -u64 gv11b_gpu_phys_addr(struct gk20a *g, - struct nvgpu_gmmu_attrs *attrs, u64 phys) +static u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys) { - if (attrs->t19x_attrs.l3_alloc) + if (attrs && attrs->t19x_attrs.l3_alloc) return phys | NVGPU_L3_ALLOC_BIT; return phys; @@ -322,6 +322,7 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; -- cgit v1.2.2 From 96615351ad11a186f5869e56acb3c1948ab7b7cc Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: gv11b: Reorg mm HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533355 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7ba8f74f..941a0bbe 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -static bool gv11b_mm_is_bar1_supported(struct gk20a *g) +bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -static int gv11b_init_mm_setup_hw(struct gk20a *g) +int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -static u64 gv11b_gpu_phys_addr(struct gk20a *g, +u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ static u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,19 +318,3 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } - -void gv11b_init_mm(struct gpu_ops *gops) -{ - gp10b_init_mm(gops); - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; - gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; - gops->mm.l2_flush = gv11b_mm_l2_flush; - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; - gops->mm.fault_info_mem_destroy = - gv11b_mm_fault_info_mem_destroy; - gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; -} -- cgit v1.2.2 From a4e095aa37ec5a6c09a8cc6477da9fa49a73cd77 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 11 Aug 2017 14:40:58 -0700 Subject: Revert "gpu: nvgpu: gv11b: Reorg mm HAL init" This reverts commit 96615351ad11a186f5869e56acb3c1948ab7b7cc, which conflicts with gv100 changes. Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537667 Reviewed-by: Shu Zhong Tested-by: Shu Zhong --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 941a0bbe..7ba8f74f 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -bool gv11b_mm_is_bar1_supported(struct gk20a *g) +static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -void gv11b_mm_remove_bar2_vm(struct gk20a *g) +static void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -int gv11b_init_mm_setup_hw(struct gk20a *g) +static int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -u64 gv11b_gpu_phys_addr(struct gk20a *g, +static u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,3 +318,19 @@ int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } + +void gv11b_init_mm(struct gpu_ops *gops) +{ + gp10b_init_mm(gops); + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; + gops->mm.init_inst_block = gv11b_init_inst_block; + gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; + gops->mm.l2_flush = gv11b_mm_l2_flush; + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; + gops->mm.fault_info_mem_destroy = + gv11b_mm_fault_info_mem_destroy; + gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; + gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; +} -- cgit v1.2.2 From 8ab6445df5b24c200ac4e346684119a85008e0e3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: Reorg mm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537754 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7ba8f74f..941a0bbe 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -static bool gv11b_mm_is_bar1_supported(struct gk20a *g) +bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -static int gv11b_init_mm_setup_hw(struct gk20a *g) +int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -static u64 gv11b_gpu_phys_addr(struct gk20a *g, +u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ static u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,19 +318,3 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } - -void gv11b_init_mm(struct gpu_ops *gops) -{ - gp10b_init_mm(gops); - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; - gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; - gops->mm.l2_flush = gv11b_mm_l2_flush; - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; - gops->mm.fault_info_mem_destroy = - gv11b_mm_fault_info_mem_destroy; - gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; -} -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 941a0bbe..6df29cb0 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include -- cgit v1.2.2 From f518304e0d8102216c7c0022cd4b66fcd844264c Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: fix GV100 hal definitions These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 6df29cb0..e452462e 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -118,7 +118,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * gmmu_fault_buf_size_v(); - err = nvgpu_dma_alloc_map_sys(vm, fb_size, + err = nvgpu_dma_alloc_map(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); if (err) { nvgpu_err(g, @@ -131,7 +131,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, HW_FAULT_BUF_STATUS_ALLOC_TRUE; *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; - err = nvgpu_dma_alloc_map_sys(vm, fb_size, + err = nvgpu_dma_alloc_map(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); if (err) { nvgpu_err(g, -- cgit v1.2.2 From d436ed36ae684986540f745a2eca7a1009be5780 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 20 Oct 2017 09:35:37 -0700 Subject: gpu: nvgpu: gv10x: alloc fault buffer in sysmem With coherency issues solved, it is no longer needed to allocate the fault buffer in vidmem as a workaround. JIRA: NVGPUGV100-36 Change-Id: I1c83e9bac61f27b75f38fce963899485afeed009 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582769 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index e452462e..6df29cb0 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -118,7 +118,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * gmmu_fault_buf_size_v(); - err = nvgpu_dma_alloc_map(vm, fb_size, + err = nvgpu_dma_alloc_map_sys(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); if (err) { nvgpu_err(g, @@ -131,7 +131,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, HW_FAULT_BUF_STATUS_ALLOC_TRUE; *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; - err = nvgpu_dma_alloc_map(vm, fb_size, + err = nvgpu_dma_alloc_map_sys(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); if (err) { nvgpu_err(g, -- cgit v1.2.2 From 0899e11d4bb630381607a0c245f72476e2e9209e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 6 Oct 2017 17:20:12 -0700 Subject: gpu: nvgpu: Cleanup generic MM code t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 6df29cb0..fdc506ac 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/mm_gk20a.h" @@ -54,7 +55,7 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct gk20a *g = gk20a_from_vm(vm); gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", - gk20a_mm_inst_block_addr(g, inst_block), inst_block->cpu_va); + nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va); g->ops.mm.init_pdb(g, inst_block, vm); @@ -191,7 +192,7 @@ void gv11b_mm_remove_bar2_vm(struct gk20a *g) gv11b_mm_mmu_hw_fault_buf_deinit(g); - gk20a_free_inst_block(g, &mm->bar2.inst_block); + nvgpu_free_inst_block(g, &mm->bar2.inst_block); nvgpu_vm_put(mm->bar2.vm); } @@ -282,7 +283,7 @@ int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; - u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); + u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); u32 reg_val; struct nvgpu_timeout timeout; u32 delay = GR_IDLE_CHECK_DEFAULT; -- cgit v1.2.2