From b07a304ba3e747c80fe3e0a16caec88c8e1e8b28 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 10 Jul 2018 09:54:10 -0700 Subject: gpu: nvgpu: Use HAL for calls from MM to FB mm_gv11b.c has several direct calls to fb_gv11b.h. Redirect them to go via a HAL. Also make sure the HALs are using parameter with correct signedness and prefix the parameter constants with NVGPU_FB_MMU_. MMU buffer table indices were also defined in fb_gv11b.h, even though the tables themselves are defined in include/nvgpu/mm.h. Move the indices to include/nvgpu/mm.h and prefix them with NVGPU_MM_MMU_. JIRA NVGPU-714 Change-Id: Ieeae7c5664b8f53f8313cfad0a771d14637caa08 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1776131 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 46 +++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 394ff0ed..c7556394 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -35,10 +35,8 @@ #include "gp10b/mc_gp10b.h" #include "mm_gv11b.h" -#include "fb_gv11b.h" #include "subctx_gv11b.h" -#include #include #define NVGPU_L3_ALLOC_BIT BIT(36) @@ -66,7 +64,7 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { - return gv11b_fb_mmu_fault_pending(g); + return g->ops.fb.mmu_fault_pending(g); } void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) @@ -79,23 +77,27 @@ void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) g->ops.fb.disable_hub_intr(g); - if ((gv11b_fb_is_fault_buf_enabled(g, NONREPLAY_REG_INDEX))) { - gv11b_fb_fault_buf_set_state_hw(g, NONREPLAY_REG_INDEX, - FAULT_BUF_DISABLED); + if ((g->ops.fb.is_fault_buf_enabled(g, + NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX))) { + g->ops.fb.fault_buf_set_state_hw(g, + NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX, + NVGPU_FB_MMU_FAULT_BUF_DISABLED); } - if ((gv11b_fb_is_fault_buf_enabled(g, REPLAY_REG_INDEX))) { - gv11b_fb_fault_buf_set_state_hw(g, REPLAY_REG_INDEX, - FAULT_BUF_DISABLED); + if ((g->ops.fb.is_fault_buf_enabled(g, + NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX))) { + g->ops.fb.fault_buf_set_state_hw(g, + NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX, + NVGPU_FB_MMU_FAULT_BUF_DISABLED); } if (nvgpu_mem_is_valid( - &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY])) + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) nvgpu_dma_unmap_free(vm, - &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); - if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[FAULT_TYPE_REPLAY])) + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY]); + if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) nvgpu_dma_unmap_free(vm, - &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY]); nvgpu_mutex_release(&g->mm.hub_isr_mutex); nvgpu_mutex_destroy(&g->mm.hub_isr_mutex); @@ -117,10 +119,10 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g) gmmu_fault_buf_size_v(); if (!nvgpu_mem_is_valid( - &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY])) { + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) { err = nvgpu_dma_alloc_map_sys(vm, fb_size, - &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY]); if (err) { nvgpu_err(g, "Error in hw mmu fault buf [0] alloc in bar2 vm "); @@ -130,9 +132,9 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g) } if (!nvgpu_mem_is_valid( - &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY])) { + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) { err = nvgpu_dma_alloc_map_sys(vm, fb_size, - &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY]); if (err) { nvgpu_err(g, "Error in hw mmu fault buf [1] alloc in bar2 vm "); @@ -145,10 +147,12 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g) static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g) { if (nvgpu_mem_is_valid( - &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY])) - gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX); - if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[FAULT_TYPE_REPLAY])) - gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX); + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) + g->ops.fb.fault_buf_configure_hw(g, + NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX); + if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) + g->ops.fb.fault_buf_configure_hw(g, + NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX); } static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) -- cgit v1.2.2