From 07d3387ceb10cdc4d4413d04b1223cbd5181438b Mon Sep 17 00:00:00 2001 From: Srirangan Date: Mon, 20 Aug 2018 16:09:12 +0530 Subject: gpu: nvgpu: gv11b: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I1562bd1b109a100af29bd147ed8b56463b6a8e63 Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1796674 Reviewed-by: svc-misra-checker Reviewed-by: Scott Long GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index b8272a92..73b7dae7 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -56,8 +56,9 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.init_pdb(g, inst_block, vm); - if (big_page_size && g->ops.mm.set_big_page_size) + if (big_page_size && g->ops.mm.set_big_page_size) { g->ops.mm.set_big_page_size(g, inst_block, big_page_size); + } gv11b_init_subcontext_pdb(vm, inst_block, false); } @@ -97,12 +98,14 @@ void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); if (nvgpu_mem_is_valid( - &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) { nvgpu_dma_unmap_free(vm, &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY]); - if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) + } + if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) { nvgpu_dma_unmap_free(vm, &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY]); + } nvgpu_mutex_release(&g->mm.hub_isr_mutex); nvgpu_mutex_destroy(&g->mm.hub_isr_mutex); @@ -152,12 +155,14 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g) static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g) { if (nvgpu_mem_is_valid( - &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) + &g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY])) { g->ops.fb.fault_buf_configure_hw(g, NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX); - if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) + } + if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[NVGPU_MM_MMU_FAULT_TYPE_REPLAY])) { g->ops.fb.fault_buf_configure_hw(g, NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX); + } } static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) @@ -170,8 +175,9 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) err = gv11b_mm_mmu_fault_info_buf_init(g); - if (!err) + if (!err) { gv11b_mm_mmu_hw_fault_buf_init(g); + } return err; } @@ -185,8 +191,9 @@ int gv11b_init_mm_setup_hw(struct gk20a *g) err = gk20a_init_mm_setup_hw(g); err = gv11b_mm_mmu_fault_setup_sw(g); - if (!err) + if (!err) { gv11b_mm_mmu_fault_setup_hw(g); + } nvgpu_log_fn(g, "end"); @@ -199,11 +206,12 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) g->ops.mm.fb_flush(g); gk20a_mm_l2_flush(g, invalidate); - if (g->ops.bus.bar1_bind) + if (g->ops.bus.bar1_bind) { g->ops.fb.tlb_invalidate(g, g->mm.bar1.vm->pdb.mem); - else + } else { g->ops.mm.fb_flush(g); + } } /* @@ -214,8 +222,9 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { - if (attrs && attrs->l3_alloc) + if (attrs && attrs->l3_alloc) { return phys | NVGPU_L3_ALLOC_BIT; + } return phys; } -- cgit v1.2.2