From 55a5c57bc1fd532cc6d041fdfb70d90286894b35 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 7 Apr 2016 16:57:18 -0700 Subject: gpu: nvgpu: gv11b: added initial source code Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/mc_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c new file mode 100644 index 00000000..bc0aee2e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -0,0 +1,26 @@ +/* + * GV11B master + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gp10b/mc_gp10b.h" +#include "gv11b/mc_gv11b.h" +#include "hw_mc_gv11b.h" + +void gv11b_init_mc(struct gpu_ops *gops) +{ + gp10b_init_mc(gops); +} -- cgit v1.2.2 From f00a98154ecaddf849b283dd5b7cbda0f6c8f90f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 19 Oct 2016 11:24:32 -0700 Subject: gpu: nvgpu: gv11b: enable correct interrupts Enable stall and non-stall interupts for gv11b. Support for replayable interrupts will be added later. Hub interrupts are not enabled and they will be enabled after non-replayabale fault handling is in place. JIRA GV11B-11 Change-Id: I99cc470dae9d02f92e9fb3cb49186dabfed78875 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1239337 Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index bc0aee2e..0111d6b3 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -20,7 +20,32 @@ #include "gv11b/mc_gv11b.h" #include "hw_mc_gv11b.h" +static void mc_gv11b_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); +} + void gv11b_init_mc(struct gpu_ops *gops) { gp10b_init_mc(gops); + gops->mc.intr_enable = mc_gv11b_intr_enable; } -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 0111d6b3..65aad786 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B master * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,9 +16,12 @@ #include #include "gk20a/gk20a.h" + #include "gp10b/mc_gp10b.h" -#include "gv11b/mc_gv11b.h" -#include "hw_mc_gv11b.h" + +#include "mc_gv11b.h" + +#include static void mc_gv11b_intr_enable(struct gk20a *g) { -- cgit v1.2.2 From d5fe11091b6d74016e482d9c41580924cc70f520 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 10 Mar 2017 12:18:40 -0800 Subject: gpu: nvgpu: gv11b: fix stall interrupt enablement Currently priv, pbus and ltc interrupts are enabled as non-stall but being handled in stall isr. Fix is to configure them as stall interrupt. Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1319018 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 65aad786..83c03029 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -30,8 +30,11 @@ static void mc_gv11b_intr_enable(struct gk20a *g) gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() - | eng_intr_mask; + mc_intr_pfifo_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); @@ -39,9 +42,6 @@ static void mc_gv11b_intr_enable(struct gk20a *g) 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -- cgit v1.2.2 From 7b5f1bd68d8e4b90d0d5d861dbea256d982c69e5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 13:43:40 -0800 Subject: gpu: ngpu: gv11b: support hub interrupt Hub interrupt handler will be added later JIRA GPUT19X-7 Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 83c03029..c901fd76 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -31,10 +31,12 @@ static void mc_gv11b_intr_enable(struct gk20a *g) 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_pbus_pending_f() | mc_intr_ltc_pending_f() | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); @@ -47,8 +49,14 @@ static void mc_gv11b_intr_enable(struct gk20a *g) g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); } +static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) +{ + return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); +} + void gv11b_init_mc(struct gpu_ops *gops) { gp10b_init_mc(gops); gops->mc.intr_enable = mc_gv11b_intr_enable; + gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending; } -- cgit v1.2.2 From 8c246cb18df28bac83297df2c9d0c47725b94273 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 5 May 2017 14:22:06 -0700 Subject: gpu: nvgpu: gv11b: MMU parity HWW error intr Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index c901fd76..8b8fcea0 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -20,6 +20,7 @@ #include "gp10b/mc_gp10b.h" #include "mc_gv11b.h" +#include "fb_gv11b.h" #include @@ -47,6 +48,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g) | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + + /* TODO: Enable PRI faults for HUB ECC err intr */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_ECC_UNCORRECTED); } static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) -- cgit v1.2.2 From aa05648fd6038b69d1ed841f33b24cf1875efd83 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 2 Jun 2017 09:58:23 -0700 Subject: gpu: nvgpu: gv11b: set up for enabling/handling hub intr -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 8b8fcea0..cc29f74a 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -30,6 +30,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g) gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | mc_intr_hub_pending_f() | @@ -38,20 +42,19 @@ static void mc_gv11b_intr_enable(struct gk20a *g) mc_intr_ltc_pending_f() | eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() | eng_intr_mask; + + /* TODO: Enable PRI faults for HUB ECC err intr */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); - /* TODO: Enable PRI faults for HUB ECC err intr */ - gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, - HUB_INTR_TYPE_ECC_UNCORRECTED); } static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) -- cgit v1.2.2 From 4e290320fdfe56cc2fe849720d6a01b44cace1a7 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 14:05:15 -0700 Subject: gpu: nvgpu: gv11b: Reorg mc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index cc29f74a..81e6381f 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -24,7 +24,7 @@ #include -static void mc_gv11b_intr_enable(struct gk20a *g) +void mc_gv11b_intr_enable(struct gk20a *g) { u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); @@ -57,14 +57,7 @@ static void mc_gv11b_intr_enable(struct gk20a *g) } -static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) +bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) { return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); } - -void gv11b_init_mc(struct gpu_ops *gops) -{ - gp10b_init_mc(gops); - gops->mc.intr_enable = mc_gv11b_intr_enable; - gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending; -} -- cgit v1.2.2 From 2f0838af1b8a73dc976837dfa568281d47628a37 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 14:30:57 -0700 Subject: gpu: nvgpu: gv11b: Move gops.mc's non-fp members Move non-function pointer members out of the mc substruct of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. gops.mc.intr_mask_restore is now mc_intr_mask_restore Jira NVGPU-74 Change-Id: I789087704fb5e6338f6010f18457948d0ee6c630 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509604 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 81e6381f..59263e54 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -34,7 +34,7 @@ void mc_gv11b_intr_enable(struct gk20a *g) 0xffffffff); gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | mc_intr_hub_pending_f() | mc_intr_priv_ring_pending_f() | @@ -42,7 +42,7 @@ void mc_gv11b_intr_enable(struct gk20a *g) mc_intr_ltc_pending_f() | eng_intr_mask; - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() | eng_intr_mask; @@ -50,10 +50,10 @@ void mc_gv11b_intr_enable(struct gk20a *g) gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); } -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 59263e54..dab304e2 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include -- cgit v1.2.2 From 72b51a129fda4a89f226aad7c99f062977a07189 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 22 Sep 2017 15:07:13 -0700 Subject: gpu: nvgpu: gv11b: detect stall intr during preemption Check for interrupts or hangs while waiting for the preempt to complete. During pbdma/eng preempt done polling, any stalling interrupts relating to the runlist must be detected and handled in order for the preemption to complete. When PBDMA fault or CE fault occurs, the PBDMA will save out automatically. TSG related to the context in which the fault occurred will not be scheduled again until the fault is handled. In the case of some other issue requiring the engine to be reset, TSG will need to be manually preempted. In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to switch out. SW must handle these interrupts according to the relevant handling procedure before the PBDMA preempt can complete. Opt for eng reset instead of waiting for preemption to be finished when there is any stall interrupt pending during engine context preempt completion. Bug 200277163 Bug 1945121 Change-Id: Icaef79e3046d82987b8486d15cbfc8365aa26f2e Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1522914 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index dab304e2..74c5c4d6 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -70,3 +70,23 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) { return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); } + +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) +{ + u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + u32 stall_intr, eng_intr_mask; + + eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); + if (mc_intr_0 & eng_intr_mask) + return true; + + stall_intr = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f(); + if (mc_intr_0 & stall_intr) + return true; + + return false; +} -- cgit v1.2.2