From 8c246cb18df28bac83297df2c9d0c47725b94273 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 5 May 2017 14:22:06 -0700 Subject: gpu: nvgpu: gv11b: MMU parity HWW error intr Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index c901fd76..8b8fcea0 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -20,6 +20,7 @@ #include "gp10b/mc_gp10b.h" #include "mc_gv11b.h" +#include "fb_gv11b.h" #include @@ -47,6 +48,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g) | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + + /* TODO: Enable PRI faults for HUB ECC err intr */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_ECC_UNCORRECTED); } static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) -- cgit v1.2.2