From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/ltc_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c new file mode 100644 index 00000000..df2b0f68 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -0,0 +1,26 @@ +/* + * GV11B LTC + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gp10b/ltc_gp10b.h" +#include "gv11b/ltc_gv11b.h" +#include "hw_ltc_gv11b.h" + +void gv11b_init_ltc(struct gpu_ops *gops) +{ + gp10b_init_ltc(gops); +} -- cgit v1.2.2 From a674eeee419a68e27bec63e46200036f5f33c8ff Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 13 Jan 2017 14:24:36 -0800 Subject: gpu: nvgpu: gv11b: Support Stencil ZBC Pre-GP10X All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds). Clears for these kinds typically happen in two phases, depth phase and stencil phase. The depth clears can be compressed or ZBC-ed, whereas the stencil part is always uncompressed. Stencil ZBC in GP10X For GP10X both the depth and the stencil data for these packed kinds can be ZBC cleared. A given tile will be a cross product of the following states for depth and stencil. Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0, ZBC index 1 Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2 JIRA GV11B-9 Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1235520 Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index df2b0f68..c0e46be3 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B LTC * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,7 +20,26 @@ #include "gv11b/ltc_gv11b.h" #include "hw_ltc_gv11b.h" +/* + * Sets the ZBC stencil for the passed index. + */ +static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, + struct zbc_entry *stencil_val, + u32 index) +{ + u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; + + gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), + ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); + + gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), + stencil_val->depth); + + gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); +} + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); + gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; } -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index c0e46be3..85ff33d2 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -13,12 +13,13 @@ * more details. */ -#include - #include "gk20a/gk20a.h" + #include "gp10b/ltc_gp10b.h" -#include "gv11b/ltc_gv11b.h" -#include "hw_ltc_gv11b.h" + +#include "ltc_gv11b.h" + +#include /* * Sets the ZBC stencil for the passed index. -- cgit v1.2.2 From 434b1c588b9c8d61ac413b0c9ae402b483deb68b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 28 Feb 2017 16:17:04 -0800 Subject: gpu: nvgpu: gv11b: handle l2 related changes Implemented gv11b specific l2 state init and Configured ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info: - cbc_num_active_ltcs is read only for gv11b, so did not write any data to that field. - enforced serilized access to l2 from sysmem and peermem. - nvlink connected peer trafic sent through l2 JIRA GV11B-71 Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1312831 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 85ff33d2..70919f24 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -20,6 +20,8 @@ #include "ltc_gv11b.h" #include +#include +#include /* * Sets the ZBC stencil for the passed index. @@ -39,8 +41,44 @@ static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); } +static void gv11b_ltc_init_fs_state(struct gk20a *g) +{ + u32 ltc_intr; + u32 reg; + + gk20a_dbg_info("initialize gv11b l2"); + + g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); + g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); + gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); + + reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); + reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(true) + | ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); + gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); + + gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), + gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | + ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); + + /* Disable LTC interrupts */ + reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); + reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); + + /* Enable ECC interrupts */ + ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | + ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), + ltc_intr); +} + + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; + gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; } -- cgit v1.2.2 From 26cd7b3d822b0b759468300777ff6e43cb5f0f7e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 3 Mar 2017 11:59:29 -0800 Subject: gpu: nvgpu: gv11b: ltc related changes There is no peermem access for gv11b nvlink. So no need to enable peermem access through l2. Implemented gv11b specific ltc_cbc_fix_config function to read correct num_active_ltcs. JIRA GV11B-71 Change-Id: I348ce3bbf42e864341494e386b6f33478badb3a8 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1315148 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 70919f24..daad8718 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -53,8 +53,7 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); - reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(true) - | ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); + reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), @@ -75,10 +74,24 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } +u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) +{ + u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); + + if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2) + return base * 2; + else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) { + gk20a_err(dev_from_gk20a(g), + "Invalid number of active ltcs: %08x\n", val); + } + return base; +} + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; + gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; } -- cgit v1.2.2 From 6dabea9882ee965041cf42c95e8b2bcff95fbfa0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Apr 2017 11:09:13 -0700 Subject: gpu: nvgpu: gv11b: Use new error macros gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert the last remaining user of old macros to new ones. JIRA NVGPU-16 Change-Id: Ib665cfb395fe46ac988ed14d67adef885098e524 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1462968 Reviewed-by: Alex Waterman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index daad8718..415266af 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -81,8 +81,7 @@ u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2) return base * 2; else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) { - gk20a_err(dev_from_gk20a(g), - "Invalid number of active ltcs: %08x\n", val); + nvgpu_err(g, "Invalid number of active ltcs: %08x\n", val); } return base; } -- cgit v1.2.2 From 92895a57a733cffe9f4318be9a5064c9e32350e1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 27 Apr 2017 11:02:41 -0700 Subject: gpu: nvgpu: gv11b: fix error for static code analysis Functions that are not declared in header files are made static Bug 200299572 Change-Id: Ibf9e9cc9f48ad9ceaa202d1bb7ed57724057cda0 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1471538 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 415266af..c1398f92 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -74,7 +74,7 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } -u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) +static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); -- cgit v1.2.2 From 9b95bb9c4ed56b8bd8028d38d0705181076f04e3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 May 2017 12:29:19 -0600 Subject: gpu: nvgpu: remove duplicate \n from log messages nvgpu_log/info/warn/err() internally add a \n to the end of the message. Hence, callers should not include a \n at the end of the message. Doing so results in duplicate \n being printed, which ends up creating empty log messages. Remove the duplicate \n from all messages. Bug 1928311 Change-Id: I21c141934a125e0cc0cead9fb19fa6502235cf06 Signed-off-by: Stephen Warren Reviewed-on: http://git-master/r/1487233 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index c1398f92..23beca5d 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -81,7 +81,7 @@ static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2) return base * 2; else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) { - nvgpu_err(g, "Invalid number of active ltcs: %08x\n", val); + nvgpu_err(g, "Invalid number of active ltcs: %08x", val); } return base; } -- cgit v1.2.2 From 6bc36bded05ee497a474e5a718c49dc33eb235f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 22 May 2017 16:38:49 -0700 Subject: gpu: nvgpu: L2 cache tag ECC support Adding support for L2 cache tag ECC error handling JIRA: GPUT19X-112 Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1489029 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 107 ++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 23beca5d..b8a97ce3 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -20,6 +20,7 @@ #include "ltc_gv11b.h" #include +#include #include #include @@ -74,6 +75,111 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } +static void gv11b_ltc_isr(struct gk20a *g) +{ + u32 mc_intr, ltc_intr3; + unsigned int ltc, slice; + u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); + u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + u32 ltc_corrected, ltc_uncorrected; + + mc_intr = gk20a_readl(g, mc_intr_ltc_r()); + for (ltc = 0; ltc < g->ltc_count; ltc++) { + if ((mc_intr & 1 << ltc) == 0) + continue; + ltc_corrected = ltc_uncorrected = 0; + + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + u32 offset = ltc_stride * ltc + lts_stride * slice; + ltc_intr3 = gk20a_readl(g, ltc_ltc0_lts0_intr3_r() + + offset); + + /* Detect and handle ECC PARITY errors */ + + if (ltc_intr3 & + (ltc_ltcs_ltss_intr3_ecc_uncorrected_m() | + ltc_ltcs_ltss_intr3_ecc_corrected_m())) { + + ecc_status = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_status_r() + + offset); + ecc_addr = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_address_r() + + offset); + corrected_cnt = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset); + uncorrected_cnt = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset); + + corrected_delta = + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(corrected_cnt); + uncorrected_delta = + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(uncorrected_cnt); + corrected_overflow = ecc_status & + ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) { + gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); + } + if ((uncorrected_delta > 0) || uncorrected_overflow) { + gk20a_writel(g, + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); + } + + gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, + ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); + + /* update counters per slice */ + if (corrected_overflow) + corrected_delta += (0x1UL << ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()); + + ltc_corrected += corrected_delta; + ltc_uncorrected += uncorrected_delta; + nvgpu_log(g, gpu_dbg_intr, + "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3); + + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) + nvgpu_log(g, gpu_dbg_intr, "rstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()) + nvgpu_log(g, gpu_dbg_intr, "rstg ecc error uncorrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()) + nvgpu_log(g, gpu_dbg_intr, "tstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()) + nvgpu_log(g, gpu_dbg_intr, "tstg ecc error uncorrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()) + nvgpu_log(g, gpu_dbg_intr, "dstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()) + nvgpu_log(g, gpu_dbg_intr, "dstg ecc error uncorrected"); + + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + + } + + } + g->ecc.ltc.t19x.l2_cache_corrected_err_count.counters[ltc] += + ltc_corrected; + g->ecc.ltc.t19x.l2_cache_uncorrected_err_count.counters[ltc] += + ltc_uncorrected; + + } + + /* fallback to other interrupts */ + gp10b_ltc_isr(g); +} + static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); @@ -93,4 +199,5 @@ void gv11b_init_ltc(struct gpu_ops *gops) gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; + gops->ltc.isr = gv11b_ltc_isr; } -- cgit v1.2.2 From 3bf38954c2cd794485ed1bac50df8e61ad1100eb Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 17 May 2017 20:03:22 -0700 Subject: gpu: nvgpu: gv11b: move cbc init to mmu from ltc Added cbc_init in fb and removed cbc_init from ltc. Also avoid writing into read only registers in ltc. GPUT19X-70 GPUT19X-116 Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1484525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b8a97ce3..5b98b0aa 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -53,10 +53,6 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); - reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); - reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); - gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); - gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); @@ -200,4 +196,5 @@ void gv11b_init_ltc(struct gpu_ops *gops) gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; gops->ltc.isr = gv11b_ltc_isr; + gops->ltc.init_cbc = NULL; } -- cgit v1.2.2 From c37a7a577a5cf4732a32c7747f244aab19bdeaec Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 2 Jun 2017 18:08:27 -0700 Subject: gpu: nvgpu: gv11b: ltc reset seqeunce change Access ltc registers only after bringing ltc out reset. Earlier ltc bought out of reset in fb_reset which is later than accessing ltc registers. GPUT19X-70 Change-Id: Id3b0ac4ed8787a994b7a5848598e4989154a0940 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1495167 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 5b98b0aa..38986382 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -22,6 +22,7 @@ #include #include #include +#include #include /* @@ -49,6 +50,13 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) gk20a_dbg_info("initialize gv11b l2"); + g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | + mc_enable_l2_enabled_f()); + + reg = gk20a_readl(g, mc_elpg_enable_r()); + reg |= mc_elpg_enable_l2_enabled_f(); + gk20a_writel(g, mc_elpg_enable_r(), reg); + g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); -- cgit v1.2.2 From a64984e7592bcd60a2dad1be8f1d24700a2e54de Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 22 Jun 2017 16:46:48 -0700 Subject: gpu: nvgpu: Reorganize ltc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If8760efb7d8e94b63dc6f1fe9efec4ddf49c0b29 Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1507563 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 38986382..b1d85c5a 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -14,7 +14,6 @@ */ #include "gk20a/gk20a.h" - #include "gp10b/ltc_gp10b.h" #include "ltc_gv11b.h" @@ -28,7 +27,7 @@ /* * Sets the ZBC stencil for the passed index. */ -static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, +void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, struct zbc_entry *stencil_val, u32 index) { @@ -43,7 +42,7 @@ static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); } -static void gv11b_ltc_init_fs_state(struct gk20a *g) +void gv11b_ltc_init_fs_state(struct gk20a *g) { u32 ltc_intr; u32 reg; @@ -79,7 +78,7 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } -static void gv11b_ltc_isr(struct gk20a *g) +void gv11b_ltc_isr(struct gk20a *g) { u32 mc_intr, ltc_intr3; unsigned int ltc, slice; @@ -184,7 +183,7 @@ static void gv11b_ltc_isr(struct gk20a *g) gp10b_ltc_isr(g); } -static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) +u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); @@ -195,14 +194,3 @@ static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) } return base; } - - -void gv11b_init_ltc(struct gpu_ops *gops) -{ - gp10b_init_ltc(gops); - gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; - gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; - gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; - gops->ltc.isr = gv11b_ltc_isr; - gops->ltc.init_cbc = NULL; -} -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b1d85c5a..a199e024 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" -- cgit v1.2.2