From 6bc36bded05ee497a474e5a718c49dc33eb235f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 22 May 2017 16:38:49 -0700 Subject: gpu: nvgpu: L2 cache tag ECC support Adding support for L2 cache tag ECC error handling JIRA: GPUT19X-112 Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1489029 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 107 ++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 23beca5d..b8a97ce3 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -20,6 +20,7 @@ #include "ltc_gv11b.h" #include +#include #include #include @@ -74,6 +75,111 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } +static void gv11b_ltc_isr(struct gk20a *g) +{ + u32 mc_intr, ltc_intr3; + unsigned int ltc, slice; + u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); + u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + u32 ltc_corrected, ltc_uncorrected; + + mc_intr = gk20a_readl(g, mc_intr_ltc_r()); + for (ltc = 0; ltc < g->ltc_count; ltc++) { + if ((mc_intr & 1 << ltc) == 0) + continue; + ltc_corrected = ltc_uncorrected = 0; + + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + u32 offset = ltc_stride * ltc + lts_stride * slice; + ltc_intr3 = gk20a_readl(g, ltc_ltc0_lts0_intr3_r() + + offset); + + /* Detect and handle ECC PARITY errors */ + + if (ltc_intr3 & + (ltc_ltcs_ltss_intr3_ecc_uncorrected_m() | + ltc_ltcs_ltss_intr3_ecc_corrected_m())) { + + ecc_status = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_status_r() + + offset); + ecc_addr = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_address_r() + + offset); + corrected_cnt = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset); + uncorrected_cnt = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset); + + corrected_delta = + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(corrected_cnt); + uncorrected_delta = + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(uncorrected_cnt); + corrected_overflow = ecc_status & + ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) { + gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); + } + if ((uncorrected_delta > 0) || uncorrected_overflow) { + gk20a_writel(g, + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); + } + + gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, + ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); + + /* update counters per slice */ + if (corrected_overflow) + corrected_delta += (0x1UL << ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()); + + ltc_corrected += corrected_delta; + ltc_uncorrected += uncorrected_delta; + nvgpu_log(g, gpu_dbg_intr, + "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3); + + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) + nvgpu_log(g, gpu_dbg_intr, "rstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()) + nvgpu_log(g, gpu_dbg_intr, "rstg ecc error uncorrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()) + nvgpu_log(g, gpu_dbg_intr, "tstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()) + nvgpu_log(g, gpu_dbg_intr, "tstg ecc error uncorrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()) + nvgpu_log(g, gpu_dbg_intr, "dstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()) + nvgpu_log(g, gpu_dbg_intr, "dstg ecc error uncorrected"); + + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + + } + + } + g->ecc.ltc.t19x.l2_cache_corrected_err_count.counters[ltc] += + ltc_corrected; + g->ecc.ltc.t19x.l2_cache_uncorrected_err_count.counters[ltc] += + ltc_uncorrected; + + } + + /* fallback to other interrupts */ + gp10b_ltc_isr(g); +} + static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); @@ -93,4 +199,5 @@ void gv11b_init_ltc(struct gpu_ops *gops) gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; + gops->ltc.isr = gv11b_ltc_isr; } -- cgit v1.2.2